75 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e8, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16# LLVM-MCA-RISCV-SEW E87vdiv.vv v8, v8, v128vsetvli zero, a0, e64, m1, tu, mu9# LLVM-MCA-RISCV-SEW E6410vdiv.vv v8, v8, v1211 12# CHECK: Iterations: 113# CHECK-NEXT: Instructions: 414# CHECK-NEXT: Total Cycles: 26115# CHECK-NEXT: Total uOps: 416 17# CHECK: Dispatch Width: 218# CHECK-NEXT: uOps Per Cycle: 0.0219# CHECK-NEXT: IPC: 0.0220# CHECK-NEXT: Block RThroughput: 258.021 22# CHECK: Instruction Info:23# CHECK-NEXT: [1]: #uOps24# CHECK-NEXT: [2]: Latency25# CHECK-NEXT: [3]: RThroughput26# CHECK-NEXT: [4]: MayLoad27# CHECK-NEXT: [5]: MayStore28# CHECK-NEXT: [6]: HasSideEffects (U)29 30# CHECK: [1] [2] [3] [4] [5] [6] Instructions:31# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu32# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1233# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu34# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1235 36# CHECK: Resources:37# CHECK-NEXT: [0] - VLEN512SiFive7FDiv38# CHECK-NEXT: [1] - VLEN512SiFive7IDiv39# CHECK-NEXT: [2] - VLEN512SiFive7PipeA40# CHECK-NEXT: [3] - VLEN512SiFive7PipeB41# CHECK-NEXT: [4] - VLEN512SiFive7VA42# CHECK-NEXT: [5] - VLEN512SiFive7VCQ43# CHECK-NEXT: [6] - VLEN512SiFive7VL44# CHECK-NEXT: [7] - VLEN512SiFive7VS45 46# CHECK: Resource pressure per iteration:47# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]48# CHECK-NEXT: - - 2.00 - 258.00 2.00 - -49 50# CHECK: Resource pressure by instruction:51# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:52# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu53# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1254# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu55# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1256 57# CHECK: Timeline view:58# CHECK-NEXT: Index 012359 60# CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu61# CHECK-NEXT: Truncated display due to cycle limit62 63# CHECK: Average Wait times (based on the timeline view):64# CHECK-NEXT: [0]: Executions65# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue66# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready67# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage68 69# CHECK: [0] [1] [2] [3]70# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu71# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1272# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu73# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1274# CHECK-NEXT: 1 0.0 0.0 0.0 <total>75