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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s3 4vsetvli zero, a0, e8, m2, tu, mu5# LLVM-MCA-RISCV-LMUL M26vadd.vv v12, v12, v127vsetvli zero, a0, e8, m1, tu, mu8# LLVM-MCA-RISCV-LMUL M19vadd.vv v12, v12, v1210vsetvli zero, a0, e8, m8, tu, mu11# LLVM-MCA-RISCV-LMUL M812vadd.vv v12, v12, v1213 14# CHECK: Iterations: 115# CHECK-NEXT: Instructions: 616# CHECK-NEXT: Total Cycles: 4217# CHECK-NEXT: Total uOps: 618 19# CHECK: Dispatch Width: 220# CHECK-NEXT: uOps Per Cycle: 0.1421# CHECK-NEXT: IPC: 0.1422# CHECK-NEXT: Block RThroughput: 51.023 24# CHECK: Instruction Info:25# CHECK-NEXT: [1]: #uOps26# CHECK-NEXT: [2]: Latency27# CHECK-NEXT: [3]: RThroughput28# CHECK-NEXT: [4]: MayLoad29# CHECK-NEXT: [5]: MayStore30# CHECK-NEXT: [6]: HasSideEffects (U)31 32# CHECK: [1] [2] [3] [4] [5] [6] Instructions:33# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu34# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v1235# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu36# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v1237# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu38# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v1239 40# CHECK: Resources:41# CHECK-NEXT: [0] - VLEN512SiFive7FDiv42# CHECK-NEXT: [1] - VLEN512SiFive7IDiv43# CHECK-NEXT: [2] - VLEN512SiFive7PipeA44# CHECK-NEXT: [3] - VLEN512SiFive7PipeB45# CHECK-NEXT: [4] - VLEN512SiFive7VA46# CHECK-NEXT: [5] - VLEN512SiFive7VCQ47# CHECK-NEXT: [6] - VLEN512SiFive7VL48# CHECK-NEXT: [7] - VLEN512SiFive7VS49 50# CHECK: Resource pressure per iteration:51# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]52# CHECK-NEXT: - - 3.00 - 51.00 3.00 - -53 54# CHECK: Resource pressure by instruction:55# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:56# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu57# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v1258# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu59# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v1260# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu61# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v1262 63# CHECK: Timeline view:64# CHECK-NEXT: 0123456789 012345678965# CHECK-NEXT: Index 0123456789 0123456789 0166 67# CHECK: [0,0] DeeE . . . . . . . .. vsetvli zero, a0, e8, m2, tu, mu68# CHECK-NEXT: [0,1] . DeeeE . . . . . . .. vadd.vv v12, v12, v1269# CHECK-NEXT: [0,2] . DeeE . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu70# CHECK-NEXT: [0,3] . . . . DeeeE. . . .. vadd.vv v12, v12, v1271# CHECK-NEXT: [0,4] . . . . .DeeE. . . .. vsetvli zero, a0, e8, m8, tu, mu72# CHECK-NEXT: [0,5] . . . . . . . . DeeeE vadd.vv v12, v12, v1273 74# CHECK: Average Wait times (based on the timeline view):75# CHECK-NEXT: [0]: Executions76# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue77# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready78# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage79 80# CHECK: [0] [1] [2] [3]81# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu82# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1283# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu84# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1285# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu86# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1287# CHECK-NEXT: 1 0.0 0.0 0.0 <total>88