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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s3 4# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)5# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV6# SPEC.7vsetvli zero, zero, e32, mf2, tu, mu8vdiv.vv v12, v12, v129vsetvli zero, zero, e8, mf8, tu, mu10vdiv.vv v12, v12, v1211 12# CHECK: Iterations: 113# CHECK-NEXT: Instructions: 414# CHECK-NEXT: Total Cycles: 8515# CHECK-NEXT: Total uOps: 416 17# CHECK: Dispatch Width: 218# CHECK-NEXT: uOps Per Cycle: 0.0519# CHECK-NEXT: IPC: 0.0520# CHECK-NEXT: Block RThroughput: 82.021 22# CHECK: Instruction Info:23# CHECK-NEXT: [1]: #uOps24# CHECK-NEXT: [2]: Latency25# CHECK-NEXT: [3]: RThroughput26# CHECK-NEXT: [4]: MayLoad27# CHECK-NEXT: [5]: MayStore28# CHECK-NEXT: [6]: HasSideEffects (U)29 30# CHECK: [1] [2] [3] [4] [5] [6] Instructions:31# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu32# CHECK-NEXT: 1 64 64.00 vdiv.vv v12, v12, v1233# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu34# CHECK-NEXT: 1 16 16.00 vdiv.vv v12, v12, v1235 36# CHECK: Resources:37# CHECK-NEXT: [0] - VLEN512SiFive7FDiv38# CHECK-NEXT: [1] - VLEN512SiFive7IDiv39# CHECK-NEXT: [2] - VLEN512SiFive7PipeA40# CHECK-NEXT: [3] - VLEN512SiFive7PipeB41# CHECK-NEXT: [4] - VLEN512SiFive7VA42# CHECK-NEXT: [5] - VLEN512SiFive7VCQ43# CHECK-NEXT: [6] - VLEN512SiFive7VL44# CHECK-NEXT: [7] - VLEN512SiFive7VS45 46# CHECK: Resource pressure per iteration:47# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]48# CHECK-NEXT: - - 2.00 - 82.00 2.00 - -49 50# CHECK: Resource pressure by instruction:51# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:52# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu53# CHECK-NEXT: - - - - 65.00 1.00 - - vdiv.vv v12, v12, v1254# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu55# CHECK-NEXT: - - - - 17.00 1.00 - - vdiv.vv v12, v12, v1256