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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 --timeline -iterations=1 < %s | FileCheck %s3 4# LLVM-MCA-LATENCY 205add a0, a0, a06 7# CHECK: Iterations: 18# CHECK-NEXT: Instructions: 19# CHECK-NEXT: Total Cycles: 2110# CHECK-NEXT: Total uOps: 111 12# CHECK: Dispatch Width: 213# CHECK-NEXT: uOps Per Cycle: 0.0514# CHECK-NEXT: IPC: 0.0515# CHECK-NEXT: Block RThroughput: 0.516 17# CHECK: Instruction Info:18# CHECK-NEXT: [1]: #uOps19# CHECK-NEXT: [2]: Latency20# CHECK-NEXT: [3]: RThroughput21# CHECK-NEXT: [4]: MayLoad22# CHECK-NEXT: [5]: MayStore23# CHECK-NEXT: [6]: HasSideEffects (U)24 25# CHECK: [1] [2] [3] [4] [5] [6] Instructions:26# CHECK-NEXT: 1 3 0.50 add a0, a0, a027 28# CHECK: Resources:29# CHECK-NEXT: [0] - VLEN512SiFive7FDiv30# CHECK-NEXT: [1] - VLEN512SiFive7IDiv31# CHECK-NEXT: [2] - VLEN512SiFive7PipeA32# CHECK-NEXT: [3] - VLEN512SiFive7PipeB33# CHECK-NEXT: [4] - VLEN512SiFive7VA34# CHECK-NEXT: [5] - VLEN512SiFive7VCQ35# CHECK-NEXT: [6] - VLEN512SiFive7VL36# CHECK-NEXT: [7] - VLEN512SiFive7VS37 38# CHECK: Resource pressure per iteration:39# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]40# CHECK-NEXT: - - - 1.00 - - - -41 42# CHECK: Resource pressure by instruction:43# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:44# CHECK-NEXT: - - - 1.00 - - - - add a0, a0, a045 46# CHECK: Timeline view:47# CHECK-NEXT: 012345678948# CHECK-NEXT: Index 0123456789 049 50# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeE add a0, a0, a051 52# CHECK: Average Wait times (based on the timeline view):53# CHECK-NEXT: [0]: Executions54# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue55# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready56# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage57 58# CHECK: [0] [1] [2] [3]59# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add a0, a0, a060