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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e8, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16vadd.vv v12, v12, v127 8# CHECK: Iterations: 19# CHECK-NEXT: Instructions: 210# CHECK-NEXT: Total Cycles: 811# CHECK-NEXT: Total uOps: 212 13# CHECK: Dispatch Width: 214# CHECK-NEXT: uOps Per Cycle: 0.2515# CHECK-NEXT: IPC: 0.2516# CHECK-NEXT: Block RThroughput: 3.017 18# CHECK: Instruction Info:19# CHECK-NEXT: [1]: #uOps20# CHECK-NEXT: [2]: Latency21# CHECK-NEXT: [3]: RThroughput22# CHECK-NEXT: [4]: MayLoad23# CHECK-NEXT: [5]: MayStore24# CHECK-NEXT: [6]: HasSideEffects (U)25 26# CHECK: [1] [2] [3] [4] [5] [6] Instructions:27# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu28# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1229 30# CHECK: Resources:31# CHECK-NEXT: [0] - VLEN512SiFive7FDiv32# CHECK-NEXT: [1] - VLEN512SiFive7IDiv33# CHECK-NEXT: [2] - VLEN512SiFive7PipeA34# CHECK-NEXT: [3] - VLEN512SiFive7PipeB35# CHECK-NEXT: [4] - VLEN512SiFive7VA36# CHECK-NEXT: [5] - VLEN512SiFive7VCQ37# CHECK-NEXT: [6] - VLEN512SiFive7VL38# CHECK-NEXT: [7] - VLEN512SiFive7VS39 40# CHECK: Resource pressure per iteration:41# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]42# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -43 44# CHECK: Resource pressure by instruction:45# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:46# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu47# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1248 49# CHECK: Timeline view:50# CHECK-NEXT: Index 0123456751 52# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu53# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v1254 55# CHECK: Average Wait times (based on the timeline view):56# CHECK-NEXT: [0]: Executions57# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue58# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready59# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage60 61# CHECK: [0] [1] [2] [3]62# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu63# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1264# CHECK-NEXT: 1 0.0 0.0 0.0 <total>65