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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4# LLVM-MCA-BEGIN foo5vsetvli zero, a0, e8, m1, tu, mu6# LLVM-MCA-RISCV-LMUL M17vadd.vv v12, v12, v128# LLVM-MCA-END foo9 10# CHECK: [0] Code Region - foo11 12# CHECK: Iterations: 113# CHECK-NEXT: Instructions: 214# CHECK-NEXT: Total Cycles: 815# CHECK-NEXT: Total uOps: 216 17# CHECK: Dispatch Width: 218# CHECK-NEXT: uOps Per Cycle: 0.2519# CHECK-NEXT: IPC: 0.2520# CHECK-NEXT: Block RThroughput: 3.021 22# CHECK: Instruction Info:23# CHECK-NEXT: [1]: #uOps24# CHECK-NEXT: [2]: Latency25# CHECK-NEXT: [3]: RThroughput26# CHECK-NEXT: [4]: MayLoad27# CHECK-NEXT: [5]: MayStore28# CHECK-NEXT: [6]: HasSideEffects (U)29 30# CHECK: [1] [2] [3] [4] [5] [6] Instructions:31# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu32# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1233 34# CHECK: Resources:35# CHECK-NEXT: [0] - VLEN512SiFive7FDiv36# CHECK-NEXT: [1] - VLEN512SiFive7IDiv37# CHECK-NEXT: [2] - VLEN512SiFive7PipeA38# CHECK-NEXT: [3] - VLEN512SiFive7PipeB39# CHECK-NEXT: [4] - VLEN512SiFive7VA40# CHECK-NEXT: [5] - VLEN512SiFive7VCQ41# CHECK-NEXT: [6] - VLEN512SiFive7VL42# CHECK-NEXT: [7] - VLEN512SiFive7VS43 44# CHECK: Resource pressure per iteration:45# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]46# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -47 48# CHECK: Resource pressure by instruction:49# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:50# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu51# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1252 53# CHECK: Timeline view:54# CHECK-NEXT: Index 0123456755 56# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu57# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v1258 59# CHECK: Average Wait times (based on the timeline view):60# CHECK-NEXT: [0]: Executions61# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue62# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready63# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage64 65# CHECK: [0] [1] [2] [3]66# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu67# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1268# CHECK-NEXT: 1 0.0 0.0 0.0 <total>69