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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4# LLVM-MCA-BEGIN foo5vsetvli zero, a0, e8, m1, tu, mu6# LLVM-MCA-RISCV-LMUL M17vadd.vv v12, v12, v128# LLVM-MCA-END foo9vadd.vv v12, v12, v1210 11# CHECK: [0] Code Region - foo12 13# CHECK: Iterations: 114# CHECK-NEXT: Instructions: 215# CHECK-NEXT: Total Cycles: 816# CHECK-NEXT: Total uOps: 217 18# CHECK: Dispatch Width: 219# CHECK-NEXT: uOps Per Cycle: 0.2520# CHECK-NEXT: IPC: 0.2521# CHECK-NEXT: Block RThroughput: 3.022 23# CHECK: Instruction Info:24# CHECK-NEXT: [1]: #uOps25# CHECK-NEXT: [2]: Latency26# CHECK-NEXT: [3]: RThroughput27# CHECK-NEXT: [4]: MayLoad28# CHECK-NEXT: [5]: MayStore29# CHECK-NEXT: [6]: HasSideEffects (U)30 31# CHECK: [1] [2] [3] [4] [5] [6] Instructions:32# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu33# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1234 35# CHECK: Resources:36# CHECK-NEXT: [0] - VLEN512SiFive7FDiv37# CHECK-NEXT: [1] - VLEN512SiFive7IDiv38# CHECK-NEXT: [2] - VLEN512SiFive7PipeA39# CHECK-NEXT: [3] - VLEN512SiFive7PipeB40# CHECK-NEXT: [4] - VLEN512SiFive7VA41# CHECK-NEXT: [5] - VLEN512SiFive7VCQ42# CHECK-NEXT: [6] - VLEN512SiFive7VL43# CHECK-NEXT: [7] - VLEN512SiFive7VS44 45# CHECK: Resource pressure per iteration:46# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]47# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -48 49# CHECK: Resource pressure by instruction:50# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:51# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu52# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1253 54# CHECK: Timeline view:55# CHECK-NEXT: Index 0123456756 57# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu58# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v1259 60# CHECK: Average Wait times (based on the timeline view):61# CHECK-NEXT: [0]: Executions62# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue63# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready64# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage65 66# CHECK: [0] [1] [2] [3]67# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu68# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1269# CHECK-NEXT: 1 0.0 0.0 0.0 <total>70