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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e8, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16vadd.vv v12, v12, v127vsetvli zero, a0, e8, m1, tu, mu8# LLVM-MCA-RISCV-LMUL M19vadd.vv v12, v12, v1210vsub.vv v12, v12, v1211vsetvli zero, a0, e8, m4, tu, mu12# LLVM-MCA-RISCV-LMUL M413vadd.vv v12, v12, v1214vsub.vv v12, v12, v1215 16# CHECK: Iterations: 117# CHECK-NEXT: Instructions: 818# CHECK-NEXT: Total Cycles: 2919# CHECK-NEXT: Total uOps: 820 21# CHECK: Dispatch Width: 222# CHECK-NEXT: uOps Per Cycle: 0.2823# CHECK-NEXT: IPC: 0.2824# CHECK-NEXT: Block RThroughput: 27.025 26# CHECK: Instruction Info:27# CHECK-NEXT: [1]: #uOps28# CHECK-NEXT: [2]: Latency29# CHECK-NEXT: [3]: RThroughput30# CHECK-NEXT: [4]: MayLoad31# CHECK-NEXT: [5]: MayStore32# CHECK-NEXT: [6]: HasSideEffects (U)33 34# CHECK: [1] [2] [3] [4] [5] [6] Instructions:35# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu36# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1237# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu38# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1239# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v1240# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu41# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v1242# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v1243 44# CHECK: Resources:45# CHECK-NEXT: [0] - VLEN512SiFive7FDiv46# CHECK-NEXT: [1] - VLEN512SiFive7IDiv47# CHECK-NEXT: [2] - VLEN512SiFive7PipeA48# CHECK-NEXT: [3] - VLEN512SiFive7PipeB49# CHECK-NEXT: [4] - VLEN512SiFive7VA50# CHECK-NEXT: [5] - VLEN512SiFive7VCQ51# CHECK-NEXT: [6] - VLEN512SiFive7VL52# CHECK-NEXT: [7] - VLEN512SiFive7VS53 54# CHECK: Resource pressure per iteration:55# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]56# CHECK-NEXT: - - 3.00 - 27.00 5.00 - -57 58# CHECK: Resource pressure by instruction:59# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:60# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu61# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1262# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu63# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1264# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vv v12, v12, v1265# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu66# CHECK-NEXT: - - - - 9.00 1.00 - - vadd.vv v12, v12, v1267# CHECK-NEXT: - - - - 9.00 1.00 - - vsub.vv v12, v12, v1268 69# CHECK: Timeline view:70# CHECK-NEXT: 012345678971# CHECK-NEXT: Index 0123456789 01234567872 73# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu74# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v1275# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu76# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v1277# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v1278# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu79# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v1280# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v1281 82# CHECK: Average Wait times (based on the timeline view):83# CHECK-NEXT: [0]: Executions84# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue85# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready86# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage87 88# CHECK: [0] [1] [2] [3]89# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu90# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1291# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu92# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1293# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v1294# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m4, tu, mu95# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1296# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v1297# CHECK-NEXT: 1 0.0 0.0 0.0 <total>98