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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e64, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16# LLVM-MCA-RISCV-SEW E647vdiv.vv v8, v8, v128vsetvli zero, a0, e64, m1, tu, mu9# LLVM-MCA-RISCV-SEW E6410vdiv.vv v8, v8, v1211vdivu.vv v8, v8, v1212vsetvli zero, a0, e32, m1, tu, mu13# LLVM-MCA-RISCV-SEW E3214vdiv.vv v8, v8, v1215vdivu.vv v8, v8, v1216 17# CHECK: Iterations: 118# CHECK-NEXT: Instructions: 819# CHECK-NEXT: Total Cycles: 64820# CHECK-NEXT: Total uOps: 821 22# CHECK: Dispatch Width: 223# CHECK-NEXT: uOps Per Cycle: 0.0124# CHECK-NEXT: IPC: 0.0125# CHECK-NEXT: Block RThroughput: 645.026 27# CHECK: Instruction Info:28# CHECK-NEXT: [1]: #uOps29# CHECK-NEXT: [2]: Latency30# CHECK-NEXT: [3]: RThroughput31# CHECK-NEXT: [4]: MayLoad32# CHECK-NEXT: [5]: MayStore33# CHECK-NEXT: [6]: HasSideEffects (U)34 35# CHECK: [1] [2] [3] [4] [5] [6] Instructions:36# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu37# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1238# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu39# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1240# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v1241# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu42# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1243# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v1244 45# CHECK: Resources:46# CHECK-NEXT: [0] - VLEN512SiFive7FDiv47# CHECK-NEXT: [1] - VLEN512SiFive7IDiv48# CHECK-NEXT: [2] - VLEN512SiFive7PipeA49# CHECK-NEXT: [3] - VLEN512SiFive7PipeB50# CHECK-NEXT: [4] - VLEN512SiFive7VA51# CHECK-NEXT: [5] - VLEN512SiFive7VCQ52# CHECK-NEXT: [6] - VLEN512SiFive7VL53# CHECK-NEXT: [7] - VLEN512SiFive7VS54 55# CHECK: Resource pressure per iteration:56# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]57# CHECK-NEXT: - - 3.00 - 645.00 5.00 - -58 59# CHECK: Resource pressure by instruction:60# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:61# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu62# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1263# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu64# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1265# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v1266# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu67# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1268# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v1269 70# CHECK: Timeline view:71# CHECK-NEXT: Index 012372 73# CHECK: [0,0] DeeE vsetvli zero, a0, e64, m1, tu, mu74# CHECK-NEXT: Truncated display due to cycle limit75 76# CHECK: Average Wait times (based on the timeline view):77# CHECK-NEXT: [0]: Executions78# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue79# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready80# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage81 82# CHECK: [0] [1] [2] [3]83# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu84# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1285# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu86# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1287# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vdivu.vv v8, v8, v1288# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e32, m1, tu, mu89# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1290# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vdivu.vv v8, v8, v1291# CHECK-NEXT: 1 0.0 0.0 0.0 <total>92