71 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4# Test LMUL but no SEW falls back to worst case.5vsetvli zero, a0, e8, m1, tu, mu6# LLVM-MCA-RISCV-LMUL M17vdiv.vv v8, v8, v128# LLVM-MCA-RISCV-SEW E89vdiv.vv v8, v8, v1210 11# CHECK: Iterations: 112# CHECK-NEXT: Instructions: 313# CHECK-NEXT: Total Cycles: 26114# CHECK-NEXT: Total uOps: 315 16# CHECK: Dispatch Width: 217# CHECK-NEXT: uOps Per Cycle: 0.0118# CHECK-NEXT: IPC: 0.0119# CHECK-NEXT: Block RThroughput: 258.020 21# CHECK: Instruction Info:22# CHECK-NEXT: [1]: #uOps23# CHECK-NEXT: [2]: Latency24# CHECK-NEXT: [3]: RThroughput25# CHECK-NEXT: [4]: MayLoad26# CHECK-NEXT: [5]: MayStore27# CHECK-NEXT: [6]: HasSideEffects (U)28 29# CHECK: [1] [2] [3] [4] [5] [6] Instructions:30# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu31# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1232# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1233 34# CHECK: Resources:35# CHECK-NEXT: [0] - VLEN512SiFive7FDiv36# CHECK-NEXT: [1] - VLEN512SiFive7IDiv37# CHECK-NEXT: [2] - VLEN512SiFive7PipeA38# CHECK-NEXT: [3] - VLEN512SiFive7PipeB39# CHECK-NEXT: [4] - VLEN512SiFive7VA40# CHECK-NEXT: [5] - VLEN512SiFive7VCQ41# CHECK-NEXT: [6] - VLEN512SiFive7VL42# CHECK-NEXT: [7] - VLEN512SiFive7VS43 44# CHECK: Resource pressure per iteration:45# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]46# CHECK-NEXT: - - 1.00 - 258.00 2.00 - -47 48# CHECK: Resource pressure by instruction:49# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:50# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu51# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1252# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1253 54# CHECK: Timeline view:55# CHECK-NEXT: Index 012356 57# CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu58# CHECK-NEXT: Truncated display due to cycle limit59 60# CHECK: Average Wait times (based on the timeline view):61# CHECK-NEXT: [0]: Executions62# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue63# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready64# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage65 66# CHECK: [0] [1] [2] [3]67# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu68# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1269# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1270# CHECK-NEXT: 1 0.0 0.0 0.0 <total>71