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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e8, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16# LLVM-MCA-RISCV-SEW E87vdiv.vv v8, v8, v128 9# CHECK: Iterations: 110# CHECK-NEXT: Instructions: 211# CHECK-NEXT: Total Cycles: 13212# CHECK-NEXT: Total uOps: 213 14# CHECK: Dispatch Width: 215# CHECK-NEXT: uOps Per Cycle: 0.0216# CHECK-NEXT: IPC: 0.0217# CHECK-NEXT: Block RThroughput: 129.018 19# CHECK: Instruction Info:20# CHECK-NEXT: [1]: #uOps21# CHECK-NEXT: [2]: Latency22# CHECK-NEXT: [3]: RThroughput23# CHECK-NEXT: [4]: MayLoad24# CHECK-NEXT: [5]: MayStore25# CHECK-NEXT: [6]: HasSideEffects (U)26 27# CHECK: [1] [2] [3] [4] [5] [6] Instructions:28# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu29# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1230 31# CHECK: Resources:32# CHECK-NEXT: [0] - VLEN512SiFive7FDiv33# CHECK-NEXT: [1] - VLEN512SiFive7IDiv34# CHECK-NEXT: [2] - VLEN512SiFive7PipeA35# CHECK-NEXT: [3] - VLEN512SiFive7PipeB36# CHECK-NEXT: [4] - VLEN512SiFive7VA37# CHECK-NEXT: [5] - VLEN512SiFive7VCQ38# CHECK-NEXT: [6] - VLEN512SiFive7VL39# CHECK-NEXT: [7] - VLEN512SiFive7VS40 41# CHECK: Resource pressure per iteration:42# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]43# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -44 45# CHECK: Resource pressure by instruction:46# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:47# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu48# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1249 50# CHECK: Timeline view:51# CHECK-NEXT: Index 012352 53# CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu54# CHECK-NEXT: Truncated display due to cycle limit55 56# CHECK: Average Wait times (based on the timeline view):57# CHECK-NEXT: [0]: Executions58# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue59# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready60# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage61 62# CHECK: [0] [1] [2] [3]63# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu64# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1265# CHECK-NEXT: 1 0.0 0.0 0.0 <total>66