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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4# llvm-mca should use `WorstCase` SEW if there is no instrument that specifies5# which SEW to use. On sifive-x280, `WorstCase` SEW is the smallest SEW, so6# the first vadd.vv should use E8 and the second should use E64.7 8vdiv.vv v8, v8, v129vsetvli zero, a0, e8, m8, tu, mu10# LLVM-MCA-RISCV-LMUL M811# LLVM-MCA-RISCV-SEW E6412vdiv.vv v8, v8, v1213 14# CHECK: Iterations: 115# CHECK-NEXT: Instructions: 316# CHECK-NEXT: Total Cycles: 205017# CHECK-NEXT: Total uOps: 318 19# CHECK: Dispatch Width: 220# CHECK-NEXT: uOps Per Cycle: 0.0021# CHECK-NEXT: IPC: 0.0022# CHECK-NEXT: Block RThroughput: 2050.023 24# CHECK: Instruction Info:25# CHECK-NEXT: [1]: #uOps26# CHECK-NEXT: [2]: Latency27# CHECK-NEXT: [3]: RThroughput28# CHECK-NEXT: [4]: MayLoad29# CHECK-NEXT: [5]: MayStore30# CHECK-NEXT: [6]: HasSideEffects (U)31 32# CHECK: [1] [2] [3] [4] [5] [6] Instructions:33# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v1234# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu35# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v1236 37# CHECK: Resources:38# CHECK-NEXT: [0] - VLEN512SiFive7FDiv39# CHECK-NEXT: [1] - VLEN512SiFive7IDiv40# CHECK-NEXT: [2] - VLEN512SiFive7PipeA41# CHECK-NEXT: [3] - VLEN512SiFive7PipeB42# CHECK-NEXT: [4] - VLEN512SiFive7VA43# CHECK-NEXT: [5] - VLEN512SiFive7VCQ44# CHECK-NEXT: [6] - VLEN512SiFive7VL45# CHECK-NEXT: [7] - VLEN512SiFive7VS46 47# CHECK: Resource pressure per iteration:48# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]49# CHECK-NEXT: - - 1.00 - 2050.00 2.00 - -50 51# CHECK: Resource pressure by instruction:52# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:53# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v1254# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu55# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v1256 57# CHECK: Timeline view:58# CHECK-NEXT: Index 059# CHECK-NEXT: Truncated display due to cycle limit60 61# CHECK: Average Wait times (based on the timeline view):62# CHECK-NEXT: [0]: Executions63# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue64# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready65# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage66 67# CHECK: [0] [1] [2] [3]68# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1269# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu70# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1271# CHECK-NEXT: 1 0.0 0.0 0.0 <total>72