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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4# LLVM-MCA-BEGIN foo5vsetvli zero, a0, e64, m1, tu, mu6# LLVM-MCA-RISCV-LMUL M17# LLVM-MCA-RISCV-SEW E648vdiv.vv v8, v8, v129# LLVM-MCA-END foo10vdiv.vv v8, v8, v1211 12# CHECK: [0] Code Region - foo13 14# CHECK: Iterations: 115# CHECK-NEXT: Instructions: 216# CHECK-NEXT: Total Cycles: 13217# CHECK-NEXT: Total uOps: 218 19# CHECK: Dispatch Width: 220# CHECK-NEXT: uOps Per Cycle: 0.0221# CHECK-NEXT: IPC: 0.0222# CHECK-NEXT: Block RThroughput: 129.023 24# CHECK: Instruction Info:25# CHECK-NEXT: [1]: #uOps26# CHECK-NEXT: [2]: Latency27# CHECK-NEXT: [3]: RThroughput28# CHECK-NEXT: [4]: MayLoad29# CHECK-NEXT: [5]: MayStore30# CHECK-NEXT: [6]: HasSideEffects (U)31 32# CHECK: [1] [2] [3] [4] [5] [6] Instructions:33# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu34# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1235 36# CHECK: Resources:37# CHECK-NEXT: [0] - VLEN512SiFive7FDiv38# CHECK-NEXT: [1] - VLEN512SiFive7IDiv39# CHECK-NEXT: [2] - VLEN512SiFive7PipeA40# CHECK-NEXT: [3] - VLEN512SiFive7PipeB41# CHECK-NEXT: [4] - VLEN512SiFive7VA42# CHECK-NEXT: [5] - VLEN512SiFive7VCQ43# CHECK-NEXT: [6] - VLEN512SiFive7VL44# CHECK-NEXT: [7] - VLEN512SiFive7VS45 46# CHECK: Resource pressure per iteration:47# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]48# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -49 50# CHECK: Resource pressure by instruction:51# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:52# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu53# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1254 55# CHECK: Timeline view:56# CHECK-NEXT: Index 012357 58# CHECK: [0,0] DeeE vsetvli zero, a0, e64, m1, tu, mu59# CHECK-NEXT: Truncated display due to cycle limit60 61# CHECK: Average Wait times (based on the timeline view):62# CHECK-NEXT: [0]: Executions63# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue64# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready65# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage66 67# CHECK: [0] [1] [2] [3]68# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu69# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1270# CHECK-NEXT: 1 0.0 0.0 0.0 <total>71