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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetivli zero, 8, e8, m1, tu, mu5vadd.vv v12, v12, v126vsetivli zero, 8, e8, m8, tu, mu7vadd.vv v12, v12, v128 9# CHECK: Iterations: 110# CHECK-NEXT: Instructions: 411# CHECK-NEXT: Total Cycles: 1212# CHECK-NEXT: Total uOps: 413 14# CHECK: Dispatch Width: 215# CHECK-NEXT: uOps Per Cycle: 0.3316# CHECK-NEXT: IPC: 0.3317# CHECK-NEXT: Block RThroughput: 20.018 19# CHECK: Instruction Info:20# CHECK-NEXT: [1]: #uOps21# CHECK-NEXT: [2]: Latency22# CHECK-NEXT: [3]: RThroughput23# CHECK-NEXT: [4]: MayLoad24# CHECK-NEXT: [5]: MayStore25# CHECK-NEXT: [6]: HasSideEffects (U)26 27# CHECK: [1] [2] [3] [4] [5] [6] Instructions:28# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu29# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1230# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu31# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v1232 33# CHECK: Resources:34# CHECK-NEXT: [0] - VLEN512SiFive7FDiv35# CHECK-NEXT: [1] - VLEN512SiFive7IDiv36# CHECK-NEXT: [2] - VLEN512SiFive7PipeA37# CHECK-NEXT: [3] - VLEN512SiFive7PipeB38# CHECK-NEXT: [4] - VLEN512SiFive7VA39# CHECK-NEXT: [5] - VLEN512SiFive7VCQ40# CHECK-NEXT: [6] - VLEN512SiFive7VL41# CHECK-NEXT: [7] - VLEN512SiFive7VS42 43# CHECK: Resource pressure per iteration:44# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]45# CHECK-NEXT: - - 2.00 - 20.00 2.00 - -46 47# CHECK: Resource pressure by instruction:48# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:49# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu50# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1251# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu52# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v1253 54# CHECK: Timeline view:55# CHECK-NEXT: 0156# CHECK-NEXT: Index 012345678957 58# CHECK: [0,0] DeeE . .. vsetivli zero, 8, e8, m1, tu, mu59# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v1260# CHECK-NEXT: [0,2] . DeeE .. vsetivli zero, 8, e8, m8, tu, mu61# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v1262 63# CHECK: Average Wait times (based on the timeline view):64# CHECK-NEXT: [0]: Executions65# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue66# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready67# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage68 69# CHECK: [0] [1] [2] [3]70# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu71# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1272# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m8, tu, mu73# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1274# CHECK-NEXT: 1 0.0 0.0 0.0 <total>75