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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetivli zero, 8, e8, m1, tu, mu5vdiv.vv v8, v8, v126vsetivli zero, 8, e32, m8, tu, mu7vdiv.vv v8, v8, v128 9# CHECK: Iterations: 110# CHECK-NEXT: Instructions: 411# CHECK-NEXT: Total Cycles: 115712# CHECK-NEXT: Total uOps: 413 14# CHECK: Dispatch Width: 215# CHECK-NEXT: uOps Per Cycle: 0.0016# CHECK-NEXT: IPC: 0.0017# CHECK-NEXT: Block RThroughput: 1154.018 19# CHECK: Instruction Info:20# CHECK-NEXT: [1]: #uOps21# CHECK-NEXT: [2]: Latency22# CHECK-NEXT: [3]: RThroughput23# CHECK-NEXT: [4]: MayLoad24# CHECK-NEXT: [5]: MayStore25# CHECK-NEXT: [6]: HasSideEffects (U)26 27# CHECK: [1] [2] [3] [4] [5] [6] Instructions:28# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu29# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v1230# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e32, m8, tu, mu31# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v1232 33# CHECK: Resources:34# CHECK-NEXT: [0] - VLEN512SiFive7FDiv35# CHECK-NEXT: [1] - VLEN512SiFive7IDiv36# CHECK-NEXT: [2] - VLEN512SiFive7PipeA37# CHECK-NEXT: [3] - VLEN512SiFive7PipeB38# CHECK-NEXT: [4] - VLEN512SiFive7VA39# CHECK-NEXT: [5] - VLEN512SiFive7VCQ40# CHECK-NEXT: [6] - VLEN512SiFive7VL41# CHECK-NEXT: [7] - VLEN512SiFive7VS42 43# CHECK: Resource pressure per iteration:44# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]45# CHECK-NEXT: - - 2.00 - 1154.00 2.00 - -46 47# CHECK: Resource pressure by instruction:48# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:49# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu50# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v1251# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e32, m8, tu, mu52# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v1253 54# CHECK: Timeline view:55# CHECK-NEXT: Index 012356 57# CHECK: [0,0] DeeE vsetivli zero, 8, e8, m1, tu, mu58# CHECK-NEXT: Truncated display due to cycle limit59 60# CHECK: Average Wait times (based on the timeline view):61# CHECK-NEXT: [0]: Executions62# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue63# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready64# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage65 66# CHECK: [0] [1] [2] [3]67# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu68# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1269# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e32, m8, tu, mu70# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v1271# CHECK-NEXT: 1 0.0 0.0 0.0 <total>72