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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s3 4# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)5# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV6# SPEC.7vsetvli zero, zero, e32, mf2, tu, mu8vdiv.vv v12, v12, v129vsetvli zero, zero, e8, mf8, tu, mu10vdiv.vv v12, v12, v1211 12# CHECK: Resources:13# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:114# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:115# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:116# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB17# CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:118# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:119# CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA220# CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:121# CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:122# CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:123# CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:124 25# CHECK: Instruction Info:26# CHECK-NEXT: [1]: #uOps27# CHECK-NEXT: [2]: Latency28# CHECK-NEXT: [3]: RThroughput29# CHECK-NEXT: [4]: MayLoad30# CHECK-NEXT: [5]: MayStore31# CHECK-NEXT: [6]: HasSideEffects (U)32# CHECK-NEXT: [7]: Bypass Latency33# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])34# CHECK-NEXT: [9]: LLVM Opcode Name35 36# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:37# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu38# CHECK-NEXT: 1 128 128.00 128 VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv v12, v12, v1239# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu40# CHECK-NEXT: 1 32 32.00 32 VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv v12, v12, v1241 42# CHECK: Resources:43# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv44# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv45# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA46# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeB47# CHECK-NEXT: [4] - VLEN1024X300SiFive7VA148# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA249# CHECK-NEXT: [6] - VLEN1024X300SiFive7VCQ50# CHECK-NEXT: [7] - VLEN1024X300SiFive7VL51# CHECK-NEXT: [8] - VLEN1024X300SiFive7VS52 53# CHECK: Resource pressure per iteration:54# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]55# CHECK-NEXT: - - 2.00 - 162.00 - 2.00 - -56 57# CHECK: Resource pressure by instruction:58# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:59# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu60# CHECK-NEXT: - - - - 129.00 - 1.00 - - vdiv.vv v12, v12, v1261# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu62# CHECK-NEXT: - - - - 33.00 - 1.00 - - vdiv.vv v12, v12, v1263