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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s3 4# Single-Width Integer Reductions5vsetvli zero, zero, e8, mf8, tu, mu6vredsum.vs v4, v8, v127vsetvli zero, zero, e8, mf4, tu, mu8vredsum.vs v4, v8, v129vsetvli zero, zero, e8, mf2, tu, mu10vredsum.vs v4, v8, v1211vsetvli zero, zero, e8, m1, tu, mu12vredsum.vs v4, v8, v1213vsetvli zero, zero, e8, m2, tu, mu14vredsum.vs v4, v8, v1215vsetvli zero, zero, e8, m4, tu, mu16vredsum.vs v4, v8, v1217vsetvli zero, zero, e8, m8, tu, mu18vredsum.vs v4, v8, v1219vsetvli zero, zero, e16, mf4, tu, mu20vredand.vs v4, v8, v1221vsetvli zero, zero, e16, mf2, tu, mu22vredand.vs v4, v8, v1223vsetvli zero, zero, e16, m1, tu, mu24vredand.vs v4, v8, v1225vsetvli zero, zero, e16, m2, tu, mu26vredand.vs v4, v8, v1227vsetvli zero, zero, e16, m4, tu, mu28vredand.vs v4, v8, v1229vsetvli zero, zero, e16, m8, tu, mu30vredand.vs v4, v8, v1231vsetvli zero, zero, e32, mf2, tu, mu32vredor.vs v4, v8, v1233vsetvli zero, zero, e32, m1, tu, mu34vredor.vs v4, v8, v1235vsetvli zero, zero, e32, m2, tu, mu36vredor.vs v4, v8, v1237vsetvli zero, zero, e32, m4, tu, mu38vredor.vs v4, v8, v1239vsetvli zero, zero, e32, m8, tu, mu40vredor.vs v4, v8, v1241vsetvli zero, zero, e64, m1, tu, mu42vredxor.vs v4, v8, v1243vsetvli zero, zero, e64, m2, tu, mu44vredxor.vs v4, v8, v1245vsetvli zero, zero, e64, m4, tu, mu46vredxor.vs v4, v8, v1247vsetvli zero, zero, e64, m8, tu, mu48vredxor.vs v4, v8, v1249# Single-Width Integer Min/Max Reductions50vsetvli zero, zero, e8, mf8, tu, mu51vredmaxu.vs v4, v8, v1252vsetvli zero, zero, e8, mf4, tu, mu53vredmaxu.vs v4, v8, v1254vsetvli zero, zero, e8, mf2, tu, mu55vredmaxu.vs v4, v8, v1256vsetvli zero, zero, e8, m1, tu, mu57vredmaxu.vs v4, v8, v1258vsetvli zero, zero, e8, m2, tu, mu59vredmaxu.vs v4, v8, v1260vsetvli zero, zero, e8, m4, tu, mu61vredmaxu.vs v4, v8, v1262vsetvli zero, zero, e8, m8, tu, mu63vredmaxu.vs v4, v8, v1264vsetvli zero, zero, e16, mf4, tu, mu65vredmax.vs v4, v8, v1266vsetvli zero, zero, e16, mf2, tu, mu67vredmax.vs v4, v8, v1268vsetvli zero, zero, e16, m1, tu, mu69vredmax.vs v4, v8, v1270vsetvli zero, zero, e16, m2, tu, mu71vredmax.vs v4, v8, v1272vsetvli zero, zero, e16, m4, tu, mu73vredmax.vs v4, v8, v1274vsetvli zero, zero, e16, m8, tu, mu75vredmax.vs v4, v8, v1276vsetvli zero, zero, e32, mf2, tu, mu77vredminu.vs v4, v8, v1278vsetvli zero, zero, e32, m1, tu, mu79vredminu.vs v4, v8, v1280vsetvli zero, zero, e32, m2, tu, mu81vredminu.vs v4, v8, v1282vsetvli zero, zero, e32, m4, tu, mu83vredminu.vs v4, v8, v1284vsetvli zero, zero, e32, m8, tu, mu85vredminu.vs v4, v8, v1286vsetvli zero, zero, e64, m1, tu, mu87vredmin.vs v4, v8, v1288vsetvli zero, zero, e64, m2, tu, mu89vredmin.vs v4, v8, v1290vsetvli zero, zero, e64, m4, tu, mu91vredmin.vs v4, v8, v1292vsetvli zero, zero, e64, m8, tu, mu93vredmin.vs v4, v8, v1294# Widening Integer Reductions95vsetvli zero, zero, e8, mf8, tu, mu96vwredsumu.vs v4, v8, v1297vsetvli zero, zero, e8, mf4, tu, mu98vwredsumu.vs v4, v8, v1299vsetvli zero, zero, e8, mf2, tu, mu100vwredsumu.vs v4, v8, v12101vsetvli zero, zero, e8, m1, tu, mu102vwredsumu.vs v4, v8, v12103vsetvli zero, zero, e8, m2, tu, mu104vwredsumu.vs v4, v8, v12105vsetvli zero, zero, e8, m4, tu, mu106vwredsumu.vs v4, v8, v12107vsetvli zero, zero, e8, m8, tu, mu108vwredsumu.vs v4, v8, v12109vsetvli zero, zero, e16, mf4, tu, mu110vwredsumu.vs v4, v8, v12111vsetvli zero, zero, e16, mf2, tu, mu112vwredsumu.vs v4, v8, v12113vsetvli zero, zero, e16, m1, tu, mu114vwredsumu.vs v4, v8, v12115vsetvli zero, zero, e16, m2, tu, mu116vwredsumu.vs v4, v8, v12117vsetvli zero, zero, e16, m4, tu, mu118vwredsumu.vs v4, v8, v12119vsetvli zero, zero, e16, m8, tu, mu120vwredsumu.vs v4, v8, v12121vsetvli zero, zero, e32, mf2, tu, mu122vwredsum.vs v4, v8, v12123vsetvli zero, zero, e32, m1, tu, mu124vwredsum.vs v4, v8, v12125vsetvli zero, zero, e32, m2, tu, mu126vwredsum.vs v4, v8, v12127vsetvli zero, zero, e32, m4, tu, mu128vwredsum.vs v4, v8, v12129vsetvli zero, zero, e32, m8, tu, mu130vwredsum.vs v4, v8, v12131vsetvli zero, zero, e64, m1, tu, mu132vwredsum.vs v4, v8, v12133vsetvli zero, zero, e64, m2, tu, mu134vwredsum.vs v4, v8, v12135vsetvli zero, zero, e64, m4, tu, mu136vwredsum.vs v4, v8, v12137vsetvli zero, zero, e64, m8, tu, mu138vwredsum.vs v4, v8, v12139 140# Vector Single-Width FP Reduction Instructions141# vfwredosum.vs142# SEW will not be e8, or e64143# LMUL will not be mf8144vsetvli zero, zero, e16, mf4, tu, mu145vfwredosum.vs v4, v8, v12146vsetvli zero, zero, e16, mf2, tu, mu147vfwredosum.vs v4, v8, v12148vsetvli zero, zero, e16, m1, tu, mu149vfwredosum.vs v4, v8, v12150vsetvli zero, zero, e16, m2, tu, mu151vfwredosum.vs v4, v8, v12152vsetvli zero, zero, e16, m4, tu, mu153vfwredosum.vs v4, v8, v12154vsetvli zero, zero, e16, m8, tu, mu155vfwredosum.vs v4, v8, v12156vsetvli zero, zero, e32, mf2, tu, mu157vfwredosum.vs v4, v8, v12158vsetvli zero, zero, e32, m1, tu, mu159vfwredosum.vs v4, v8, v12160vsetvli zero, zero, e32, m2, tu, mu161vfwredosum.vs v4, v8, v12162vsetvli zero, zero, e32, m4, tu, mu163vfwredosum.vs v4, v8, v12164vsetvli zero, zero, e32, m8, tu, mu165vfwredosum.vs v4, v8, v12166# vfwredusum.vs167vsetvli zero, zero, e16, mf4, tu, mu168vfwredusum.vs v4, v8, v12169vsetvli zero, zero, e16, mf2, tu, mu170vfwredusum.vs v4, v8, v12171vsetvli zero, zero, e16, m1, tu, mu172vfwredusum.vs v4, v8, v12173vsetvli zero, zero, e16, m2, tu, mu174vfwredusum.vs v4, v8, v12175vsetvli zero, zero, e16, m4, tu, mu176vfwredusum.vs v4, v8, v12177vsetvli zero, zero, e16, m8, tu, mu178vfwredusum.vs v4, v8, v12179vsetvli zero, zero, e32, mf2, tu, mu180vfwredusum.vs v4, v8, v12181vsetvli zero, zero, e32, m1, tu, mu182vfwredusum.vs v4, v8, v12183vsetvli zero, zero, e32, m2, tu, mu184vfwredusum.vs v4, v8, v12185vsetvli zero, zero, e32, m4, tu, mu186vfwredusum.vs v4, v8, v12187vsetvli zero, zero, e32, m8, tu, mu188vfwredusum.vs v4, v8, v12189 190# Single Width Floating Point Min/Max Reductions191# SEW wont be e8192# LMUL wont be mf8193vsetvli zero, zero, e16, mf4, tu, mu194vfredmax.vs v4, v8, v12195vsetvli zero, zero, e16, mf2, tu, mu196vfredmax.vs v4, v8, v12197vsetvli zero, zero, e16, m1, tu, mu198vfredmax.vs v4, v8, v12199vsetvli zero, zero, e16, m2, tu, mu200vfredmax.vs v4, v8, v12201vsetvli zero, zero, e16, m4, tu, mu202vfredmax.vs v4, v8, v12203vsetvli zero, zero, e16, m8, tu, mu204vfredmax.vs v4, v8, v12205vsetvli zero, zero, e32, mf2, tu, mu206vfredmin.vs v4, v8, v12207vsetvli zero, zero, e32, m1, tu, mu208vfredmin.vs v4, v8, v12209vsetvli zero, zero, e32, m2, tu, mu210vfredmin.vs v4, v8, v12211vsetvli zero, zero, e32, m4, tu, mu212vfredmin.vs v4, v8, v12213vsetvli zero, zero, e32, m8, tu, mu214vfredmin.vs v4, v8, v12215vsetvli zero, zero, e64, m1, tu, mu216vfredmin.vs v4, v8, v12217vsetvli zero, zero, e64, m2, tu, mu218vfredmin.vs v4, v8, v12219vsetvli zero, zero, e64, m4, tu, mu220vfredmin.vs v4, v8, v12221vsetvli zero, zero, e64, m8, tu, mu222vfredmin.vs v4, v8, v12223 224# CHECK: Resources:225# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:1226# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:1227# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:1228# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB229# CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:1230# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:1231# CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2232# CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:1233# CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:1234# CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:1235# CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:1236 237# CHECK: Instruction Info:238# CHECK-NEXT: [1]: #uOps239# CHECK-NEXT: [2]: Latency240# CHECK-NEXT: [3]: RThroughput241# CHECK-NEXT: [4]: MayLoad242# CHECK-NEXT: [5]: MayStore243# CHECK-NEXT: [6]: HasSideEffects (U)244# CHECK-NEXT: [7]: Bypass Latency245# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])246# CHECK-NEXT: [9]: LLVM Opcode Name247 248# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:249# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu250# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12251# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu252# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12253# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu254# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12255# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu256# CHECK-NEXT: 1 52 52.00 52 VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12257# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu258# CHECK-NEXT: 1 54 54.00 54 VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12259# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu260# CHECK-NEXT: 1 58 58.00 58 VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12261# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu262# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs v4, v8, v12263# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu264# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12265# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu266# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12267# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu268# CHECK-NEXT: 1 47 47.00 47 VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12269# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu270# CHECK-NEXT: 1 49 49.00 49 VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12271# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu272# CHECK-NEXT: 1 53 53.00 53 VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12273# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu274# CHECK-NEXT: 1 61 61.00 61 VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs v4, v8, v12275# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu276# CHECK-NEXT: 1 41 41.00 41 VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs v4, v8, v12277# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu278# CHECK-NEXT: 1 42 42.00 42 VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs v4, v8, v12279# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu280# CHECK-NEXT: 1 44 44.00 44 VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs v4, v8, v12281# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu282# CHECK-NEXT: 1 48 48.00 48 VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs v4, v8, v12283# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu284# CHECK-NEXT: 1 56 56.00 56 VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs v4, v8, v12285# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu286# CHECK-NEXT: 1 37 37.00 37 VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs v4, v8, v12287# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu288# CHECK-NEXT: 1 39 39.00 39 VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs v4, v8, v12289# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu290# CHECK-NEXT: 1 43 43.00 43 VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs v4, v8, v12291# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu292# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs v4, v8, v12293# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu294# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12295# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu296# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12297# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu298# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12299# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu300# CHECK-NEXT: 1 52 52.00 52 VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12301# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu302# CHECK-NEXT: 1 54 54.00 54 VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12303# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu304# CHECK-NEXT: 1 58 58.00 58 VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12305# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu306# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs v4, v8, v12307# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu308# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12309# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu310# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12311# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu312# CHECK-NEXT: 1 47 47.00 47 VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12313# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu314# CHECK-NEXT: 1 49 49.00 49 VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12315# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu316# CHECK-NEXT: 1 53 53.00 53 VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12317# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu318# CHECK-NEXT: 1 61 61.00 61 VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs v4, v8, v12319# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu320# CHECK-NEXT: 1 41 41.00 41 VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs v4, v8, v12321# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu322# CHECK-NEXT: 1 42 42.00 42 VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs v4, v8, v12323# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu324# CHECK-NEXT: 1 44 44.00 44 VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs v4, v8, v12325# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu326# CHECK-NEXT: 1 48 48.00 48 VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs v4, v8, v12327# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu328# CHECK-NEXT: 1 56 56.00 56 VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs v4, v8, v12329# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu330# CHECK-NEXT: 1 37 37.00 37 VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs v4, v8, v12331# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu332# CHECK-NEXT: 1 39 39.00 39 VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs v4, v8, v12333# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu334# CHECK-NEXT: 1 43 43.00 43 VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs v4, v8, v12335# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu336# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs v4, v8, v12337# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu338# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12339# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu340# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12341# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu342# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12343# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu344# CHECK-NEXT: 1 52 52.00 52 VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12345# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu346# CHECK-NEXT: 1 54 54.00 54 VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12347# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu348# CHECK-NEXT: 1 58 58.00 58 VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12349# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu350# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12351# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu352# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12353# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu354# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12355# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu356# CHECK-NEXT: 1 47 47.00 47 VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12357# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu358# CHECK-NEXT: 1 49 49.00 49 VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12359# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu360# CHECK-NEXT: 1 53 53.00 53 VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12361# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu362# CHECK-NEXT: 1 61 61.00 61 VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs v4, v8, v12363# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu364# CHECK-NEXT: 1 41 41.00 41 VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12365# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu366# CHECK-NEXT: 1 42 42.00 42 VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12367# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu368# CHECK-NEXT: 1 44 44.00 44 VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12369# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu370# CHECK-NEXT: 1 48 48.00 48 VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12371# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu372# CHECK-NEXT: 1 56 56.00 56 VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12373# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu374# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12375# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu376# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12377# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu378# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12379# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu380# CHECK-NEXT: 1 66 66.00 66 VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs v4, v8, v12381# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu382# CHECK-NEXT: 1 96 96.00 96 VLEN1024X300SiFive7VA1[1,97],VLEN1024X300SiFive7VA1OrVA2[1,97],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12383# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu384# CHECK-NEXT: 1 192 192.00 192 VLEN1024X300SiFive7VA1[1,193],VLEN1024X300SiFive7VA1OrVA2[1,193],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12385# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu386# CHECK-NEXT: 1 384 384.00 384 VLEN1024X300SiFive7VA1[1,385],VLEN1024X300SiFive7VA1OrVA2[1,385],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12387# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu388# CHECK-NEXT: 1 768 768.00 768 VLEN1024X300SiFive7VA1[1,769],VLEN1024X300SiFive7VA1OrVA2[1,769],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12389# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu390# CHECK-NEXT: 1 1536 1536.00 1536 VLEN1024X300SiFive7VA1[1,1537],VLEN1024X300SiFive7VA1OrVA2[1,1537],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12391# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu392# CHECK-NEXT: 1 3072 3072.00 3072 VLEN1024X300SiFive7VA1[1,3073],VLEN1024X300SiFive7VA1OrVA2[1,3073],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12393# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu394# CHECK-NEXT: 1 96 96.00 96 VLEN1024X300SiFive7VA1[1,97],VLEN1024X300SiFive7VA1OrVA2[1,97],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12395# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu396# CHECK-NEXT: 1 192 192.00 192 VLEN1024X300SiFive7VA1[1,193],VLEN1024X300SiFive7VA1OrVA2[1,193],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12397# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu398# CHECK-NEXT: 1 384 384.00 384 VLEN1024X300SiFive7VA1[1,385],VLEN1024X300SiFive7VA1OrVA2[1,385],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12399# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu400# CHECK-NEXT: 1 768 768.00 768 VLEN1024X300SiFive7VA1[1,769],VLEN1024X300SiFive7VA1OrVA2[1,769],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12401# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu402# CHECK-NEXT: 1 1536 1536.00 1536 VLEN1024X300SiFive7VA1[1,1537],VLEN1024X300SiFive7VA1OrVA2[1,1537],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs v4, v8, v12403# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu404# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12405# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu406# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12407# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu408# CHECK-NEXT: 1 47 47.00 47 VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12409# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu410# CHECK-NEXT: 1 49 49.00 49 VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12411# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu412# CHECK-NEXT: 1 53 53.00 53 VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12413# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu414# CHECK-NEXT: 1 61 61.00 61 VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12415# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu416# CHECK-NEXT: 1 41 41.00 41 VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12417# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu418# CHECK-NEXT: 1 42 42.00 42 VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12419# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu420# CHECK-NEXT: 1 44 44.00 44 VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12421# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu422# CHECK-NEXT: 1 48 48.00 48 VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12423# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu424# CHECK-NEXT: 1 56 56.00 56 VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs v4, v8, v12425# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu426# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12427# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu428# CHECK-NEXT: 1 46 46.00 46 VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12429# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu430# CHECK-NEXT: 1 47 47.00 47 VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12431# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu432# CHECK-NEXT: 1 49 49.00 49 VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12433# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu434# CHECK-NEXT: 1 53 53.00 53 VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12435# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu436# CHECK-NEXT: 1 61 61.00 61 VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs v4, v8, v12437# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu438# CHECK-NEXT: 1 41 41.00 41 VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12439# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu440# CHECK-NEXT: 1 42 42.00 42 VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12441# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu442# CHECK-NEXT: 1 44 44.00 44 VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12443# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu444# CHECK-NEXT: 1 48 48.00 48 VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12445# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu446# CHECK-NEXT: 1 56 56.00 56 VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12447# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu448# CHECK-NEXT: 1 37 37.00 37 VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12449# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu450# CHECK-NEXT: 1 39 39.00 39 VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12451# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu452# CHECK-NEXT: 1 43 43.00 43 VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12453# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu454# CHECK-NEXT: 1 51 51.00 51 VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs v4, v8, v12455 456# CHECK: Resources:457# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv458# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv459# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA460# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeB461# CHECK-NEXT: [4] - VLEN1024X300SiFive7VA1462# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA2463# CHECK-NEXT: [6] - VLEN1024X300SiFive7VCQ464# CHECK-NEXT: [7] - VLEN1024X300SiFive7VL465# CHECK-NEXT: [8] - VLEN1024X300SiFive7VS466 467# CHECK: Resource pressure per iteration:468# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]469# CHECK-NEXT: - - 103.00 - 13715.00 - 103.00 - -470 471# CHECK: Resource pressure by instruction:472# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:473# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu474# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredsum.vs v4, v8, v12475# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu476# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredsum.vs v4, v8, v12477# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu478# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredsum.vs v4, v8, v12479# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu480# CHECK-NEXT: - - - - 53.00 - 1.00 - - vredsum.vs v4, v8, v12481# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu482# CHECK-NEXT: - - - - 55.00 - 1.00 - - vredsum.vs v4, v8, v12483# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m4, tu, mu484# CHECK-NEXT: - - - - 59.00 - 1.00 - - vredsum.vs v4, v8, v12485# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m8, tu, mu486# CHECK-NEXT: - - - - 67.00 - 1.00 - - vredsum.vs v4, v8, v12487# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu488# CHECK-NEXT: - - - - 47.00 - 1.00 - - vredand.vs v4, v8, v12489# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu490# CHECK-NEXT: - - - - 47.00 - 1.00 - - vredand.vs v4, v8, v12491# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu492# CHECK-NEXT: - - - - 48.00 - 1.00 - - vredand.vs v4, v8, v12493# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu494# CHECK-NEXT: - - - - 50.00 - 1.00 - - vredand.vs v4, v8, v12495# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu496# CHECK-NEXT: - - - - 54.00 - 1.00 - - vredand.vs v4, v8, v12497# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu498# CHECK-NEXT: - - - - 62.00 - 1.00 - - vredand.vs v4, v8, v12499# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu500# CHECK-NEXT: - - - - 42.00 - 1.00 - - vredor.vs v4, v8, v12501# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu502# CHECK-NEXT: - - - - 43.00 - 1.00 - - vredor.vs v4, v8, v12503# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu504# CHECK-NEXT: - - - - 45.00 - 1.00 - - vredor.vs v4, v8, v12505# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu506# CHECK-NEXT: - - - - 49.00 - 1.00 - - vredor.vs v4, v8, v12507# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu508# CHECK-NEXT: - - - - 57.00 - 1.00 - - vredor.vs v4, v8, v12509# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu510# CHECK-NEXT: - - - - 38.00 - 1.00 - - vredxor.vs v4, v8, v12511# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu512# CHECK-NEXT: - - - - 40.00 - 1.00 - - vredxor.vs v4, v8, v12513# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m4, tu, mu514# CHECK-NEXT: - - - - 44.00 - 1.00 - - vredxor.vs v4, v8, v12515# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m8, tu, mu516# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredxor.vs v4, v8, v12517# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu518# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredmaxu.vs v4, v8, v12519# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu520# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredmaxu.vs v4, v8, v12521# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu522# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredmaxu.vs v4, v8, v12523# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu524# CHECK-NEXT: - - - - 53.00 - 1.00 - - vredmaxu.vs v4, v8, v12525# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu526# CHECK-NEXT: - - - - 55.00 - 1.00 - - vredmaxu.vs v4, v8, v12527# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m4, tu, mu528# CHECK-NEXT: - - - - 59.00 - 1.00 - - vredmaxu.vs v4, v8, v12529# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m8, tu, mu530# CHECK-NEXT: - - - - 67.00 - 1.00 - - vredmaxu.vs v4, v8, v12531# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu532# CHECK-NEXT: - - - - 47.00 - 1.00 - - vredmax.vs v4, v8, v12533# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu534# CHECK-NEXT: - - - - 47.00 - 1.00 - - vredmax.vs v4, v8, v12535# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu536# CHECK-NEXT: - - - - 48.00 - 1.00 - - vredmax.vs v4, v8, v12537# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu538# CHECK-NEXT: - - - - 50.00 - 1.00 - - vredmax.vs v4, v8, v12539# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu540# CHECK-NEXT: - - - - 54.00 - 1.00 - - vredmax.vs v4, v8, v12541# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu542# CHECK-NEXT: - - - - 62.00 - 1.00 - - vredmax.vs v4, v8, v12543# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu544# CHECK-NEXT: - - - - 42.00 - 1.00 - - vredminu.vs v4, v8, v12545# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu546# CHECK-NEXT: - - - - 43.00 - 1.00 - - vredminu.vs v4, v8, v12547# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu548# CHECK-NEXT: - - - - 45.00 - 1.00 - - vredminu.vs v4, v8, v12549# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu550# CHECK-NEXT: - - - - 49.00 - 1.00 - - vredminu.vs v4, v8, v12551# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu552# CHECK-NEXT: - - - - 57.00 - 1.00 - - vredminu.vs v4, v8, v12553# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu554# CHECK-NEXT: - - - - 38.00 - 1.00 - - vredmin.vs v4, v8, v12555# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu556# CHECK-NEXT: - - - - 40.00 - 1.00 - - vredmin.vs v4, v8, v12557# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m4, tu, mu558# CHECK-NEXT: - - - - 44.00 - 1.00 - - vredmin.vs v4, v8, v12559# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m8, tu, mu560# CHECK-NEXT: - - - - 52.00 - 1.00 - - vredmin.vs v4, v8, v12561# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu562# CHECK-NEXT: - - - - 52.00 - 1.00 - - vwredsumu.vs v4, v8, v12563# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu564# CHECK-NEXT: - - - - 52.00 - 1.00 - - vwredsumu.vs v4, v8, v12565# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu566# CHECK-NEXT: - - - - 52.00 - 1.00 - - vwredsumu.vs v4, v8, v12567# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu568# CHECK-NEXT: - - - - 53.00 - 1.00 - - vwredsumu.vs v4, v8, v12569# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu570# CHECK-NEXT: - - - - 55.00 - 1.00 - - vwredsumu.vs v4, v8, v12571# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m4, tu, mu572# CHECK-NEXT: - - - - 59.00 - 1.00 - - vwredsumu.vs v4, v8, v12573# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m8, tu, mu574# CHECK-NEXT: - - - - 67.00 - 1.00 - - vwredsumu.vs v4, v8, v12575# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu576# CHECK-NEXT: - - - - 47.00 - 1.00 - - vwredsumu.vs v4, v8, v12577# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu578# CHECK-NEXT: - - - - 47.00 - 1.00 - - vwredsumu.vs v4, v8, v12579# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu580# CHECK-NEXT: - - - - 48.00 - 1.00 - - vwredsumu.vs v4, v8, v12581# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu582# CHECK-NEXT: - - - - 50.00 - 1.00 - - vwredsumu.vs v4, v8, v12583# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu584# CHECK-NEXT: - - - - 54.00 - 1.00 - - vwredsumu.vs v4, v8, v12585# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu586# CHECK-NEXT: - - - - 62.00 - 1.00 - - vwredsumu.vs v4, v8, v12587# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu588# CHECK-NEXT: - - - - 42.00 - 1.00 - - vwredsum.vs v4, v8, v12589# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu590# CHECK-NEXT: - - - - 43.00 - 1.00 - - vwredsum.vs v4, v8, v12591# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu592# CHECK-NEXT: - - - - 45.00 - 1.00 - - vwredsum.vs v4, v8, v12593# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu594# CHECK-NEXT: - - - - 49.00 - 1.00 - - vwredsum.vs v4, v8, v12595# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu596# CHECK-NEXT: - - - - 57.00 - 1.00 - - vwredsum.vs v4, v8, v12597# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu598# CHECK-NEXT: - - - - 67.00 - 1.00 - - vwredsum.vs v4, v8, v12599# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu600# CHECK-NEXT: - - - - 67.00 - 1.00 - - vwredsum.vs v4, v8, v12601# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m4, tu, mu602# CHECK-NEXT: - - - - 67.00 - 1.00 - - vwredsum.vs v4, v8, v12603# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m8, tu, mu604# CHECK-NEXT: - - - - 67.00 - 1.00 - - vwredsum.vs v4, v8, v12605# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu606# CHECK-NEXT: - - - - 97.00 - 1.00 - - vfwredosum.vs v4, v8, v12607# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu608# CHECK-NEXT: - - - - 193.00 - 1.00 - - vfwredosum.vs v4, v8, v12609# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu610# CHECK-NEXT: - - - - 385.00 - 1.00 - - vfwredosum.vs v4, v8, v12611# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu612# CHECK-NEXT: - - - - 769.00 - 1.00 - - vfwredosum.vs v4, v8, v12613# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu614# CHECK-NEXT: - - - - 1537.00 - 1.00 - - vfwredosum.vs v4, v8, v12615# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu616# CHECK-NEXT: - - - - 3073.00 - 1.00 - - vfwredosum.vs v4, v8, v12617# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu618# CHECK-NEXT: - - - - 97.00 - 1.00 - - vfwredosum.vs v4, v8, v12619# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu620# CHECK-NEXT: - - - - 193.00 - 1.00 - - vfwredosum.vs v4, v8, v12621# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu622# CHECK-NEXT: - - - - 385.00 - 1.00 - - vfwredosum.vs v4, v8, v12623# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu624# CHECK-NEXT: - - - - 769.00 - 1.00 - - vfwredosum.vs v4, v8, v12625# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu626# CHECK-NEXT: - - - - 1537.00 - 1.00 - - vfwredosum.vs v4, v8, v12627# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu628# CHECK-NEXT: - - - - 47.00 - 1.00 - - vfwredusum.vs v4, v8, v12629# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu630# CHECK-NEXT: - - - - 47.00 - 1.00 - - vfwredusum.vs v4, v8, v12631# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu632# CHECK-NEXT: - - - - 48.00 - 1.00 - - vfwredusum.vs v4, v8, v12633# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu634# CHECK-NEXT: - - - - 50.00 - 1.00 - - vfwredusum.vs v4, v8, v12635# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu636# CHECK-NEXT: - - - - 54.00 - 1.00 - - vfwredusum.vs v4, v8, v12637# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu638# CHECK-NEXT: - - - - 62.00 - 1.00 - - vfwredusum.vs v4, v8, v12639# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu640# CHECK-NEXT: - - - - 42.00 - 1.00 - - vfwredusum.vs v4, v8, v12641# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu642# CHECK-NEXT: - - - - 43.00 - 1.00 - - vfwredusum.vs v4, v8, v12643# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu644# CHECK-NEXT: - - - - 45.00 - 1.00 - - vfwredusum.vs v4, v8, v12645# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu646# CHECK-NEXT: - - - - 49.00 - 1.00 - - vfwredusum.vs v4, v8, v12647# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu648# CHECK-NEXT: - - - - 57.00 - 1.00 - - vfwredusum.vs v4, v8, v12649# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu650# CHECK-NEXT: - - - - 47.00 - 1.00 - - vfredmax.vs v4, v8, v12651# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu652# CHECK-NEXT: - - - - 47.00 - 1.00 - - vfredmax.vs v4, v8, v12653# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu654# CHECK-NEXT: - - - - 48.00 - 1.00 - - vfredmax.vs v4, v8, v12655# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu656# CHECK-NEXT: - - - - 50.00 - 1.00 - - vfredmax.vs v4, v8, v12657# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu658# CHECK-NEXT: - - - - 54.00 - 1.00 - - vfredmax.vs v4, v8, v12659# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e16, m8, tu, mu660# CHECK-NEXT: - - - - 62.00 - 1.00 - - vfredmax.vs v4, v8, v12661# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu662# CHECK-NEXT: - - - - 42.00 - 1.00 - - vfredmin.vs v4, v8, v12663# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu664# CHECK-NEXT: - - - - 43.00 - 1.00 - - vfredmin.vs v4, v8, v12665# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu666# CHECK-NEXT: - - - - 45.00 - 1.00 - - vfredmin.vs v4, v8, v12667# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu668# CHECK-NEXT: - - - - 49.00 - 1.00 - - vfredmin.vs v4, v8, v12669# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, m8, tu, mu670# CHECK-NEXT: - - - - 57.00 - 1.00 - - vfredmin.vs v4, v8, v12671# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu672# CHECK-NEXT: - - - - 38.00 - 1.00 - - vfredmin.vs v4, v8, v12673# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu674# CHECK-NEXT: - - - - 40.00 - 1.00 - - vfredmin.vs v4, v8, v12675# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m4, tu, mu676# CHECK-NEXT: - - - - 44.00 - 1.00 - - vfredmin.vs v4, v8, v12677# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e64, m8, tu, mu678# CHECK-NEXT: - - - - 52.00 - 1.00 - - vfredmin.vs v4, v8, v12679