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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -mattr='+xsfvqmaccqoq,+xsfvqmaccdod' -instruction-tables=full -iterations=1 %s | \3# RUN: FileCheck %s4 5vsetvli zero, zero, e8, m1, ta, ma6sf.vqmacc.2x8x2 v16, v0, v87vsetvli zero, zero, e8, m2, ta, ma8sf.vqmacc.2x8x2 v16, v0, v89vsetvli zero, zero, e8, m4, ta, ma10sf.vqmacc.2x8x2 v16, v0, v811vsetvli zero, zero, e8, m8, ta, ma12sf.vqmacc.2x8x2 v16, v0, v813 14vsetvli zero, zero, e8, mf2, ta, ma15sf.vqmacc.4x8x4 v16, v0, v816vsetvli zero, zero, e8, m1, ta, ma17sf.vqmacc.4x8x4 v16, v0, v818vsetvli zero, zero, e8, m2, ta, ma19sf.vqmacc.4x8x4 v16, v0, v820vsetvli zero, zero, e8, m4, ta, ma21sf.vqmacc.4x8x4 v16, v0, v822 23# CHECK: Resources:24# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:125# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:126# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:127# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB28# CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:129# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:130# CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA231# CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:132# CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:133# CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:134# CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:135 36# CHECK: Instruction Info:37# CHECK-NEXT: [1]: #uOps38# CHECK-NEXT: [2]: Latency39# CHECK-NEXT: [3]: RThroughput40# CHECK-NEXT: [4]: MayLoad41# CHECK-NEXT: [5]: MayStore42# CHECK-NEXT: [6]: HasSideEffects (U)43# CHECK-NEXT: [7]: Bypass Latency44# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])45# CHECK-NEXT: [9]: LLVM Opcode Name46 47# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:48# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma49# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v850# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma51# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v852# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma53# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v854# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, ta, ma55# CHECK-NEXT: 1 8 16.00 8 VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v856# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, ta, ma57# CHECK-NEXT: 1 8 1.00 8 VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v858# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma59# CHECK-NEXT: 1 8 2.00 8 VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v860# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma61# CHECK-NEXT: 1 8 4.00 8 VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v862# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma63# CHECK-NEXT: 1 8 8.00 8 VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v864 65# CHECK: Resources:66# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv67# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv68# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA69# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeB70# CHECK-NEXT: [4] - VLEN1024X300SiFive7VA171# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA272# CHECK-NEXT: [6] - VLEN1024X300SiFive7VCQ73# CHECK-NEXT: [7] - VLEN1024X300SiFive7VL74# CHECK-NEXT: [8] - VLEN1024X300SiFive7VS75 76# CHECK: Resource pressure per iteration:77# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]78# CHECK-NEXT: - - 8.00 - 53.00 - 8.00 - -79 80# CHECK: Resource pressure by instruction:81# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:82# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma83# CHECK-NEXT: - - - - 3.00 - 1.00 - - sf.vqmacc.2x8x2 v16, v0, v884# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma85# CHECK-NEXT: - - - - 5.00 - 1.00 - - sf.vqmacc.2x8x2 v16, v0, v886# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma87# CHECK-NEXT: - - - - 9.00 - 1.00 - - sf.vqmacc.2x8x2 v16, v0, v888# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma89# CHECK-NEXT: - - - - 17.00 - 1.00 - - sf.vqmacc.2x8x2 v16, v0, v890# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma91# CHECK-NEXT: - - - - 2.00 - 1.00 - - sf.vqmacc.4x8x4 v16, v0, v892# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma93# CHECK-NEXT: - - - - 3.00 - 1.00 - - sf.vqmacc.4x8x4 v16, v0, v894# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma95# CHECK-NEXT: - - - - 5.00 - 1.00 - - sf.vqmacc.4x8x4 v16, v0, v896# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma97# CHECK-NEXT: - - - - 9.00 - 1.00 - - sf.vqmacc.4x8x4 v16, v0, v898