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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr7 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK3 4lw a0, 0(s0)5lw a1, 0(s0)6lw a2, 0(s0)7lw a3, 0(s0)8 9# CHECK: Iterations: 110# CHECK-NEXT: Instructions: 411# CHECK-NEXT: Total Cycles: 912# CHECK-NEXT: Total uOps: 413 14# CHECK: Dispatch Width: 215# CHECK-NEXT: uOps Per Cycle: 0.4416# CHECK-NEXT: IPC: 0.4417# CHECK-NEXT: Block RThroughput: 4.018 19# CHECK: Instruction Info:20# CHECK-NEXT: [1]: #uOps21# CHECK-NEXT: [2]: Latency22# CHECK-NEXT: [3]: RThroughput23# CHECK-NEXT: [4]: MayLoad24# CHECK-NEXT: [5]: MayStore25# CHECK-NEXT: [6]: HasSideEffects (U)26 27# CHECK: [1] [2] [3] [4] [5] [6] Instructions:28# CHECK-NEXT: 1 3 1.00 * lw a0, 0(s0)29# CHECK-NEXT: 1 3 1.00 * lw a1, 0(s0)30# CHECK-NEXT: 1 3 1.00 * lw a2, 0(s0)31# CHECK-NEXT: 1 3 1.00 * lw a3, 0(s0)32 33# CHECK: Resources:34# CHECK-NEXT: [0] - SCR7_ALU_DIV_IS35# CHECK-NEXT: [1] - SCR7_ALU_MUL_IS36# CHECK-NEXT: [2] - SCR7_DIV37# CHECK-NEXT: [3] - SCR7_FALU38# CHECK-NEXT: [4] - SCR7_FDIVSQRT39# CHECK-NEXT: [5] - SCR7_FMA40# CHECK-NEXT: [6] - SCR7_FPU_IS41# CHECK-NEXT: [7] - SCR7_LSU42# CHECK-NEXT: [8] - SCR7_MUL43 44# CHECK: Resource pressure per iteration:45# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]46# CHECK-NEXT: - - - - - - - 4.00 -47 48# CHECK: Resource pressure by instruction:49# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:50# CHECK-NEXT: - - - - - - - 1.00 - lw a0, 0(s0)51# CHECK-NEXT: - - - - - - - 1.00 - lw a1, 0(s0)52# CHECK-NEXT: - - - - - - - 1.00 - lw a2, 0(s0)53# CHECK-NEXT: - - - - - - - 1.00 - lw a3, 0(s0)54