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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-nanhu < %s | FileCheck %s3 4# Test XiangShan FuDian's cascade FMA, CPI = 35fmadd.s fa0, fa1, fa2, fa06 7# CHECK: Iterations: 1008# CHECK-NEXT: Instructions: 1009# CHECK-NEXT: Total Cycles: 30510# CHECK-NEXT: Total uOps: 10011 12# CHECK: Dispatch Width: 613# CHECK-NEXT: uOps Per Cycle: 0.3314# CHECK-NEXT: IPC: 0.3315# CHECK-NEXT: Block RThroughput: 0.316 17# CHECK: Instruction Info:18# CHECK-NEXT: [1]: #uOps19# CHECK-NEXT: [2]: Latency20# CHECK-NEXT: [3]: RThroughput21# CHECK-NEXT: [4]: MayLoad22# CHECK-NEXT: [5]: MayStore23# CHECK-NEXT: [6]: HasSideEffects (U)24 25# CHECK: [1] [2] [3] [4] [5] [6] Instructions:26# CHECK-NEXT: 1 5 0.25 fmadd.s fa0, fa1, fa2, fa027 28# CHECK: Resources:29# CHECK-NEXT: [0.0] - XS2ALU30# CHECK-NEXT: [0.1] - XS2ALU31# CHECK-NEXT: [0.2] - XS2ALU32# CHECK-NEXT: [0.3] - XS2ALU33# CHECK-NEXT: [1.0] - XS2FMAC34# CHECK-NEXT: [1.1] - XS2FMAC35# CHECK-NEXT: [1.2] - XS2FMAC36# CHECK-NEXT: [1.3] - XS2FMAC37# CHECK-NEXT: [2.0] - XS2FMISC38# CHECK-NEXT: [2.1] - XS2FMISC39# CHECK-NEXT: [3.0] - XS2LD40# CHECK-NEXT: [3.1] - XS2LD41# CHECK-NEXT: [4.0] - XS2MDU42# CHECK-NEXT: [4.1] - XS2MDU43# CHECK-NEXT: [5] - XS2MISC44# CHECK-NEXT: [6.0] - XS2ST45# CHECK-NEXT: [6.1] - XS2ST46 47# CHECK: Resource pressure per iteration:48# CHECK-NEXT: [0.0] [0.1] [0.2] [0.3] [1.0] [1.1] [1.2] [1.3] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5] [6.0] [6.1]49# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - -50 51# CHECK: Resource pressure by instruction:52# CHECK-NEXT: [0.0] [0.1] [0.2] [0.3] [1.0] [1.1] [1.2] [1.3] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5] [6.0] [6.1] Instructions:53# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - fmadd.s fa0, fa1, fa2, fa054