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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s3 4vsetvli zero, zero, e32, m2, tu, mu5vslidedown.vx v5, v7, x66 7vsetvli zero, zero, e32, m4, tu, mu8vslidedown.vx v5, v7, x69 10vsetvli zero, zero, e32, m8, tu, mu11vslidedown.vx v5, v7, x612 13vsetvli zero, zero, e32, m2, tu, mu14vslideup.vx v5, v7, x615 16vsetvli zero, zero, e32, m4, tu, mu17vslideup.vx v5, v7, x618 19vsetvli zero, zero, e32, m8, tu, mu20vslideup.vx v5, v7, x621 22vsetvli zero, zero, e32, m2, tu, mu23vslideup.vx v5, v7, x6, v0.t24 25vsetvli zero, zero, e32, m4, tu, mu26vslideup.vx v5, v7, x6, v0.t27 28vsetvli zero, zero, e32, m8, tu, mu29vslideup.vx v5, v7, x6, v0.t30 31# CHECK: Resources:32# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB33# CHECK-NEXT: [1] - AscalonFPA:134# CHECK-NEXT: [2] - AscalonFPB:135# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD36# CHECK-NEXT: [4] - AscalonFXA:137# CHECK-NEXT: [5] - AscalonFXB:138# CHECK-NEXT: [6] - AscalonFXC:239# CHECK-NEXT: [7] - AscalonFXD:240# CHECK-NEXT: [8] - AscalonLS:341# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB42# CHECK-NEXT: [10] - AscalonVA:143# CHECK-NEXT: [11] - AscalonVB:144 45# CHECK: Instruction Info:46# CHECK-NEXT: [1]: #uOps47# CHECK-NEXT: [2]: Latency48# CHECK-NEXT: [3]: RThroughput49# CHECK-NEXT: [4]: MayLoad50# CHECK-NEXT: [5]: MayStore51# CHECK-NEXT: [6]: HasSideEffects (U)52# CHECK-NEXT: [7]: Bypass Latency53# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])54# CHECK-NEXT: [9]: LLVM Opcode Name55 56# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:57# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu58# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEDOWN_VX vslidedown.vx v5, v7, t159# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu60# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEDOWN_VX vslidedown.vx v5, v7, t161# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu62# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEDOWN_VX vslidedown.vx v5, v7, t163# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu64# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEUP_VX vslideup.vx v5, v7, t165# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu66# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEUP_VX vslideup.vx v5, v7, t167# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu68# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEUP_VX vslideup.vx v5, v7, t169# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu70# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t71# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu72# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t73# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu74# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t75 76# CHECK: Resources:77# CHECK-NEXT: [0] - AscalonFPA78# CHECK-NEXT: [1] - AscalonFPB79# CHECK-NEXT: [2] - AscalonFXA80# CHECK-NEXT: [3] - AscalonFXB81# CHECK-NEXT: [4.0] - AscalonFXC82# CHECK-NEXT: [4.1] - AscalonFXC83# CHECK-NEXT: [5.0] - AscalonFXD84# CHECK-NEXT: [5.1] - AscalonFXD85# CHECK-NEXT: [6.0] - AscalonLS86# CHECK-NEXT: [6.1] - AscalonLS87# CHECK-NEXT: [6.2] - AscalonLS88# CHECK-NEXT: [7] - AscalonVA89# CHECK-NEXT: [8] - AscalonVB90 91# CHECK: Resource pressure per iteration:92# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]93# CHECK-NEXT: - - 1.50 1.50 1.50 1.50 1.50 1.50 - - - 30.00 30.0094 95# CHECK: Resource pressure by instruction:96# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:97# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu98# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslidedown.vx v5, v7, t199# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu100# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslidedown.vx v5, v7, t1101# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu102# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslidedown.vx v5, v7, t1103# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu104# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslideup.vx v5, v7, t1105# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu106# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslideup.vx v5, v7, t1107# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu108# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslideup.vx v5, v7, t1109# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu110# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslideup.vx v5, v7, t1, v0.t111# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu112# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslideup.vx v5, v7, t1, v0.t113# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu114# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslideup.vx v5, v7, t1, v0.t115