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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -lqueue=2 -iterations=2 -resource-pressure=false -timeline -timeline-max-cycles=104 < %s | FileCheck %s3 4int35stmxcsr (%rsp)6 7# CHECK: Iterations: 28# CHECK-NEXT: Instructions: 49# CHECK-NEXT: Total Cycles: 10310# CHECK-NEXT: Total uOps: 611 12# CHECK: Dispatch Width: 413# CHECK-NEXT: uOps Per Cycle: 0.0614# CHECK-NEXT: IPC: 0.0415# CHECK-NEXT: Block RThroughput: 18.016 17# CHECK: Instruction Info:18# CHECK-NEXT: [1]: #uOps19# CHECK-NEXT: [2]: Latency20# CHECK-NEXT: [3]: RThroughput21# CHECK-NEXT: [4]: MayLoad22# CHECK-NEXT: [5]: MayStore23# CHECK-NEXT: [6]: HasSideEffects (U)24 25# CHECK: [1] [2] [3] [4] [5] [6] Instructions:26# CHECK-NEXT: 1 100 0.50 * * U int327# CHECK-NEXT: 2 1 18.00 * U stmxcsr (%rsp)28 29# CHECK: Timeline view:30# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 012345678931# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 01232 33# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER int334# CHECK-NEXT: [0,1] DeE---------------------------------------------------------------------------------------------------R stmxcsr (%rsp)35# CHECK-NEXT: [1,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER int336# CHECK-NEXT: [1,1] .D=================eE---------------------------------------------------------------------------------R stmxcsr (%rsp)37 38# CHECK: Average Wait times (based on the timeline view):39# CHECK-NEXT: [0]: Executions40# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue41# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready42# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage43 44# CHECK: [0] [1] [2] [3]45# CHECK-NEXT: 0. 2 1.0 0.5 0.0 int346# CHECK-NEXT: 1. 2 9.5 9.0 90.0 stmxcsr (%rsp)47# CHECK-NEXT: 2 5.3 4.8 45.0 <total>48