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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -register-file-size=5 -iterations=2 -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s3 4idiv %eax5 6# CHECK: Iterations: 27# CHECK-NEXT: Instructions: 28# CHECK-NEXT: Total Cycles: 429# CHECK-NEXT: Total uOps: 410 11# CHECK: Dispatch Width: 412# CHECK-NEXT: uOps Per Cycle: 0.1013# CHECK-NEXT: IPC: 0.0514# CHECK-NEXT: Block RThroughput: 25.015 16# CHECK: Instruction Info:17# CHECK-NEXT: [1]: #uOps18# CHECK-NEXT: [2]: Latency19# CHECK-NEXT: [3]: RThroughput20# CHECK-NEXT: [4]: MayLoad21# CHECK-NEXT: [5]: MayStore22# CHECK-NEXT: [6]: HasSideEffects (U)23 24# CHECK: [1] [2] [3] [4] [5] [6] Instructions:25# CHECK-NEXT: 2 14 25.00 U idivl %eax26 27# CHECK: Dynamic Dispatch Stall Cycles:28# CHECK-NEXT: RAT - Register unavailable: 16 (38.1%)29# CHECK-NEXT: RCU - Retire tokens unavailable: 030# CHECK-NEXT: SCHEDQ - Scheduler full: 031# CHECK-NEXT: LQ - Load queue full: 032# CHECK-NEXT: SQ - Store queue full: 033# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 034# CHECK-NEXT: USH - Uncategorised Structural Hazard: 035 36# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:37# CHECK-NEXT: [# dispatched], [# cycles]38# CHECK-NEXT: 0, 40 (95.2%)39# CHECK-NEXT: 2, 2 (4.8%)40 41# CHECK: Register File statistics:42# CHECK-NEXT: Total number of mappings created: 643# CHECK-NEXT: Max number of mappings used: 344 45# CHECK: * Register File #1 -- PdFpuPRF:46# CHECK-NEXT: Number of physical registers: 16047# CHECK-NEXT: Total number of mappings created: 048# CHECK-NEXT: Max number of mappings used: 049 50# CHECK: * Register File #2 -- PdIntegerPRF:51# CHECK-NEXT: Number of physical registers: 9652# CHECK-NEXT: Total number of mappings created: 653# CHECK-NEXT: Max number of mappings used: 354 55# CHECK: Resources:56# CHECK-NEXT: [0.0] - PdAGLU0157# CHECK-NEXT: [0.1] - PdAGLU0158# CHECK-NEXT: [1] - PdBranch59# CHECK-NEXT: [2] - PdCount60# CHECK-NEXT: [3] - PdDiv61# CHECK-NEXT: [4] - PdEX062# CHECK-NEXT: [5] - PdEX163# CHECK-NEXT: [6] - PdFPCVT64# CHECK-NEXT: [7.0] - PdFPFMA65# CHECK-NEXT: [7.1] - PdFPFMA66# CHECK-NEXT: [8.0] - PdFPMAL67# CHECK-NEXT: [8.1] - PdFPMAL68# CHECK-NEXT: [9] - PdFPMMA69# CHECK-NEXT: [10] - PdFPSTO70# CHECK-NEXT: [11] - PdFPU071# CHECK-NEXT: [12] - PdFPU172# CHECK-NEXT: [13] - PdFPU273# CHECK-NEXT: [14] - PdFPU374# CHECK-NEXT: [15] - PdFPXBR75# CHECK-NEXT: [16.0] - PdLoad76# CHECK-NEXT: [16.1] - PdLoad77# CHECK-NEXT: [17] - PdMul78# CHECK-NEXT: [18] - PdStore79 80# CHECK: Resource pressure per iteration:81# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7.0] [7.1] [8.0] [8.1] [9] [10] [11] [12] [13] [14] [15] [16.0] [16.1] [17] [18]82# CHECK-NEXT: - - - - 25.00 - 1.00 - - - - - - - - - - - - - - - -83 84# CHECK: Resource pressure by instruction:85# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7.0] [7.1] [8.0] [8.1] [9] [10] [11] [12] [13] [14] [15] [16.0] [16.1] [17] [18] Instructions:86# CHECK-NEXT: - - - - 25.00 - 1.00 - - - - - - - - - - - - - - - - idivl %eax87 88# CHECK: Timeline view:89# CHECK-NEXT: 0123456789 012345678990# CHECK-NEXT: Index 0123456789 0123456789 0191 92# CHECK: [0,0] DeeeeeeeeeeeeeeER . . . . .. idivl %eax93# CHECK-NEXT: [1,0] . . . .D=========eeeeeeeeeeeeeeER idivl %eax94 95# CHECK: Average Wait times (based on the timeline view):96# CHECK-NEXT: [0]: Executions97# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue98# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready99# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage100 101# CHECK: [0] [1] [2] [3]102# CHECK-NEXT: 0. 2 5.5 5.5 0.0 idivl %eax103