71 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=22 -dispatch-stats -register-file-stats -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s3 4idiv %eax5 6# CHECK: Iterations: 227# CHECK-NEXT: Instructions: 228# CHECK-NEXT: Total Cycles: 5429# CHECK-NEXT: Total uOps: 4410 11# CHECK: Dispatch Width: 412# CHECK-NEXT: uOps Per Cycle: 0.0813# CHECK-NEXT: IPC: 0.0414# CHECK-NEXT: Block RThroughput: 25.015 16# CHECK: Instruction Info:17# CHECK-NEXT: [1]: #uOps18# CHECK-NEXT: [2]: Latency19# CHECK-NEXT: [3]: RThroughput20# CHECK-NEXT: [4]: MayLoad21# CHECK-NEXT: [5]: MayStore22# CHECK-NEXT: [6]: HasSideEffects (U)23 24# CHECK: [1] [2] [3] [4] [5] [6] Instructions:25# CHECK-NEXT: 2 14 25.00 U idivl %eax26 27# CHECK: Dynamic Dispatch Stall Cycles:28# CHECK-NEXT: RAT - Register unavailable: 029# CHECK-NEXT: RCU - Retire tokens unavailable: 030# CHECK-NEXT: SCHEDQ - Scheduler full: 031# CHECK-NEXT: LQ - Load queue full: 032# CHECK-NEXT: SQ - Store queue full: 033# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 034# CHECK-NEXT: USH - Uncategorised Structural Hazard: 035 36# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:37# CHECK-NEXT: [# dispatched], [# cycles]38# CHECK-NEXT: 0, 531 (98.0%)39# CHECK-NEXT: 4, 11 (2.0%)40 41# CHECK: Register File statistics:42# CHECK-NEXT: Total number of mappings created: 6643# CHECK-NEXT: Max number of mappings used: 6644 45# CHECK: * Register File #1 -- PdFpuPRF:46# CHECK-NEXT: Number of physical registers: 16047# CHECK-NEXT: Total number of mappings created: 048# CHECK-NEXT: Max number of mappings used: 049 50# CHECK: * Register File #2 -- PdIntegerPRF:51# CHECK-NEXT: Number of physical registers: 9652# CHECK-NEXT: Total number of mappings created: 6653# CHECK-NEXT: Max number of mappings used: 6654 55# CHECK: Timeline view:56# CHECK-NEXT: 0123456789 0123456789 012345678957# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012345658 59# CHECK: [0,0] DeeeeeeeeeeeeeeER . . . . . . . . . .. idivl %eax60# CHECK-NEXT: [1,0] D=========================eeeeeeeeeeeeeeER . . . . .. idivl %eax61# CHECK-NEXT: [2,0] .D=================================================eeeeeeeeeeeeeeER idivl %eax62 63# CHECK: Average Wait times (based on the timeline view):64# CHECK-NEXT: [0]: Executions65# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue66# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready67# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage68 69# CHECK: [0] [1] [2] [3]70# CHECK-NEXT: 0. 3 25.7 7.7 0.0 idivl %eax71