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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s3 4## Sets register RAX.5imulq $5, %rcx, %rax6 7## Kills the previous definition of RAX.8## The upper portion of RAX is cleared.9lzcnt %ecx, %eax10 11## The AND can start immediately after the LZCNT.12## It doesn't need to wait for the IMUL.13and %rcx, %rax14bsf %rax, %rcx15 16# CHECK: Iterations: 10017# CHECK-NEXT: Instructions: 40018# CHECK-NEXT: Total Cycles: 66319# CHECK-NEXT: Total uOps: 100020 21# CHECK: Dispatch Width: 222# CHECK-NEXT: uOps Per Cycle: 1.5123# CHECK-NEXT: IPC: 0.6024# CHECK-NEXT: Block RThroughput: 5.025 26# CHECK: Instruction Info:27# CHECK-NEXT: [1]: #uOps28# CHECK-NEXT: [2]: Latency29# CHECK-NEXT: [3]: RThroughput30# CHECK-NEXT: [4]: MayLoad31# CHECK-NEXT: [5]: MayStore32# CHECK-NEXT: [6]: HasSideEffects (U)33 34# CHECK: [1] [2] [3] [4] [5] [6] Instructions:35# CHECK-NEXT: 1 6 4.00 imulq $5, %rcx, %rax36# CHECK-NEXT: 1 1 0.50 lzcntl %ecx, %eax37# CHECK-NEXT: 1 1 0.50 andq %rcx, %rax38# CHECK-NEXT: 7 4 4.00 bsfq %rax, %rcx39 40# CHECK: Timeline view:41# CHECK-NEXT: 01234542# CHECK-NEXT: Index 012345678943 44# CHECK: [0,0] DeeeeeeER . . imulq $5, %rcx, %rax45# CHECK-NEXT: [0,1] DeE-----R . . lzcntl %ecx, %eax46# CHECK-NEXT: [0,2] .DeE-----R. . andq %rcx, %rax47# CHECK-NEXT: [0,3] . DeeeeE-R. . bsfq %rax, %rcx48# CHECK-NEXT: [1,0] . D=eeeeeeER. imulq $5, %rcx, %rax49# CHECK-NEXT: [1,1] . .D=eE----R. lzcntl %ecx, %eax50# CHECK-NEXT: [1,2] . .D==eE----R andq %rcx, %rax51# CHECK-NEXT: [1,3] . . D==eeeeER bsfq %rax, %rcx52 53# CHECK: Average Wait times (based on the timeline view):54# CHECK-NEXT: [0]: Executions55# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue56# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready57# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage58 59# CHECK: [0] [1] [2] [3]60# CHECK-NEXT: 0. 2 1.5 0.5 0.0 imulq $5, %rcx, %rax61# CHECK-NEXT: 1. 2 1.5 1.0 4.5 lzcntl %ecx, %eax62# CHECK-NEXT: 2. 2 2.0 0.0 4.5 andq %rcx, %rax63# CHECK-NEXT: 3. 2 2.0 0.0 0.5 bsfq %rax, %rcx64# CHECK-NEXT: 2 1.8 0.4 2.4 <total>65