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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -register-file-size=5 -iterations=2 -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s3 4idiv %eax5 6# CHECK: Iterations: 27# CHECK-NEXT: Instructions: 28# CHECK-NEXT: Total Cycles: 559# CHECK-NEXT: Total uOps: 410 11# CHECK: Dispatch Width: 212# CHECK-NEXT: uOps Per Cycle: 0.0713# CHECK-NEXT: IPC: 0.0414# CHECK-NEXT: Block RThroughput: 25.015 16# CHECK: Instruction Info:17# CHECK-NEXT: [1]: #uOps18# CHECK-NEXT: [2]: Latency19# CHECK-NEXT: [3]: RThroughput20# CHECK-NEXT: [4]: MayLoad21# CHECK-NEXT: [5]: MayStore22# CHECK-NEXT: [6]: HasSideEffects (U)23 24# CHECK: [1] [2] [3] [4] [5] [6] Instructions:25# CHECK-NEXT: 2 25 25.00 U idivl %eax26 27# CHECK: Dynamic Dispatch Stall Cycles:28# CHECK-NEXT: RAT - Register unavailable: 26 (47.3%)29# CHECK-NEXT: RCU - Retire tokens unavailable: 030# CHECK-NEXT: SCHEDQ - Scheduler full: 031# CHECK-NEXT: LQ - Load queue full: 032# CHECK-NEXT: SQ - Store queue full: 033# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 034# CHECK-NEXT: USH - Uncategorised Structural Hazard: 035 36# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:37# CHECK-NEXT: [# dispatched], [# cycles]38# CHECK-NEXT: 0, 53 (96.4%)39# CHECK-NEXT: 2, 2 (3.6%)40 41# CHECK: Register File statistics:42# CHECK-NEXT: Total number of mappings created: 643# CHECK-NEXT: Max number of mappings used: 344 45# CHECK: * Register File #1 -- JFpuPRF:46# CHECK-NEXT: Number of physical registers: 7247# CHECK-NEXT: Total number of mappings created: 048# CHECK-NEXT: Max number of mappings used: 049 50# CHECK: * Register File #2 -- JIntegerPRF:51# CHECK-NEXT: Number of physical registers: 6452# CHECK-NEXT: Total number of mappings created: 653# CHECK-NEXT: Max number of mappings used: 354 55# CHECK: Resources:56# CHECK-NEXT: [0] - JALU057# CHECK-NEXT: [1] - JALU158# CHECK-NEXT: [2] - JDiv59# CHECK-NEXT: [3] - JFPA60# CHECK-NEXT: [4] - JFPM61# CHECK-NEXT: [5] - JFPU062# CHECK-NEXT: [6] - JFPU163# CHECK-NEXT: [7] - JLAGU64# CHECK-NEXT: [8] - JMul65# CHECK-NEXT: [9] - JSAGU66# CHECK-NEXT: [10] - JSTC67# CHECK-NEXT: [11] - JVALU068# CHECK-NEXT: [12] - JVALU169# CHECK-NEXT: [13] - JVIMUL70 71# CHECK: Resource pressure per iteration:72# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]73# CHECK-NEXT: - 1.00 25.00 - - - - - - - - - - -74 75# CHECK: Resource pressure by instruction:76# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:77# CHECK-NEXT: - 1.00 25.00 - - - - - - - - - - - idivl %eax78 79# CHECK: Timeline view:80# CHECK-NEXT: 0123456789 0123456789 0123481# CHECK-NEXT: Index 0123456789 0123456789 012345678982 83# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . idivl %eax84# CHECK-NEXT: [1,0] . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeeeER idivl %eax85 86# CHECK: Average Wait times (based on the timeline view):87# CHECK-NEXT: [0]: Executions88# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue89# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready90# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage91 92# CHECK: [0] [1] [2] [3]93# CHECK-NEXT: 0. 2 1.0 1.0 0.0 idivl %eax94