37 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s3 4prefetch (%rax)5prefetchw (%rax)6 7# CHECK: Instruction Info:8# CHECK-NEXT: [1]: #uOps9# CHECK-NEXT: [2]: Latency10# CHECK-NEXT: [3]: RThroughput11# CHECK-NEXT: [4]: MayLoad12# CHECK-NEXT: [5]: MayStore13# CHECK-NEXT: [6]: HasSideEffects (U)14 15# CHECK: [1] [2] [3] [4] [5] [6] Instructions:16# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)17# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)18 19# CHECK: Resources:20# CHECK-NEXT: [0] - SBDivider21# CHECK-NEXT: [1] - SBFPDivider22# CHECK-NEXT: [2] - SBPort023# CHECK-NEXT: [3] - SBPort124# CHECK-NEXT: [4] - SBPort425# CHECK-NEXT: [5] - SBPort526# CHECK-NEXT: [6.0] - SBPort2327# CHECK-NEXT: [6.1] - SBPort2328 29# CHECK: Resource pressure per iteration:30# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]31# CHECK-NEXT: - - - - - - 1.00 1.0032 33# CHECK: Resource pressure by instruction:34# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:35# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax)36# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax)37