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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 -dispatch-stats < %s | FileCheck %s3 4cmpxchg16b (%rsi)5 6# CHECK: Iterations: 1007# CHECK-NEXT: Instructions: 1008# CHECK-NEXT: Total Cycles: 22039# CHECK-NEXT: Total uOps: 190010 11# CHECK: Dispatch Width: 412# CHECK-NEXT: uOps Per Cycle: 0.8613# CHECK-NEXT: IPC: 0.0514# CHECK-NEXT: Block RThroughput: 4.815 16# CHECK: Instruction Info:17# CHECK-NEXT: [1]: #uOps18# CHECK-NEXT: [2]: Latency19# CHECK-NEXT: [3]: RThroughput20# CHECK-NEXT: [4]: MayLoad21# CHECK-NEXT: [5]: MayStore22# CHECK-NEXT: [6]: HasSideEffects (U)23 24# CHECK: [1] [2] [3] [4] [5] [6] Instructions:25# CHECK-NEXT: 19 22 4.00 * * cmpxchg16b (%rsi)26 27# CHECK: Dynamic Dispatch Stall Cycles:28# CHECK-NEXT: RAT - Register unavailable: 029# CHECK-NEXT: RCU - Retire tokens unavailable: 1487 (67.5%)30# CHECK-NEXT: SCHEDQ - Scheduler full: 031# CHECK-NEXT: LQ - Load queue full: 032# CHECK-NEXT: SQ - Store queue full: 033# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 034# CHECK-NEXT: USH - Uncategorised Structural Hazard: 035 36# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:37# CHECK-NEXT: [# dispatched], [# cycles]38# CHECK-NEXT: 0, 1703 (77.3%)39# CHECK-NEXT: 3, 100 (4.5%)40# CHECK-NEXT: 4, 400 (18.2%)41 42# CHECK: Resources:43# CHECK-NEXT: [0] - HWDivider44# CHECK-NEXT: [1] - HWFPDivider45# CHECK-NEXT: [2] - HWPort046# CHECK-NEXT: [3] - HWPort147# CHECK-NEXT: [4] - HWPort248# CHECK-NEXT: [5] - HWPort349# CHECK-NEXT: [6] - HWPort450# CHECK-NEXT: [7] - HWPort551# CHECK-NEXT: [8] - HWPort652# CHECK-NEXT: [9] - HWPort753 54# CHECK: Resource pressure per iteration:55# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]56# CHECK-NEXT: - - 2.00 6.00 0.66 0.67 1.00 4.00 4.00 0.6757 58# CHECK: Resource pressure by instruction:59# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:60# CHECK-NEXT: - - 2.00 6.00 0.66 0.67 1.00 4.00 4.00 0.67 cmpxchg16b (%rsi)61 62# CHECK: Timeline view:63# CHECK-NEXT: 0123456789 0123456789 012345678964# CHECK-NEXT: Index 0123456789 0123456789 0123456789 01234567865 66# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeER. . . . . . . . . . cmpxchg16b (%rsi)67# CHECK-NEXT: [1,0] . D=================eeeeeeeeeeeeeeeeeeeeeeER . . . . . cmpxchg16b (%rsi)68# CHECK-NEXT: [2,0] . . D==================================eeeeeeeeeeeeeeeeeeeeeeER cmpxchg16b (%rsi)69 70# CHECK: Average Wait times (based on the timeline view):71# CHECK-NEXT: [0]: Executions72# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue73# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready74# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage75 76# CHECK: [0] [1] [2] [3]77# CHECK-NEXT: 0. 3 18.0 0.3 0.0 cmpxchg16b (%rsi)78