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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 < %s | FileCheck %s3 4# Code snippet taken from PR48024.5 6stmxcsr -4(%rsp)7movl $-24577, %eax # imm = 0x9FFF8andl -4(%rsp), %eax9movl %eax, -8(%rsp)10ldmxcsr -8(%rsp)11retq12 13# CHECK: Iterations: 10014# CHECK-NEXT: Instructions: 60015# CHECK-NEXT: Total Cycles: 80916# CHECK-NEXT: Total uOps: 130017 18# CHECK: Dispatch Width: 419# CHECK-NEXT: uOps Per Cycle: 1.6120# CHECK-NEXT: IPC: 0.7421# CHECK-NEXT: Block RThroughput: 3.322 23# CHECK: Instruction Info:24# CHECK-NEXT: [1]: #uOps25# CHECK-NEXT: [2]: Latency26# CHECK-NEXT: [3]: RThroughput27# CHECK-NEXT: [4]: MayLoad28# CHECK-NEXT: [5]: MayStore29# CHECK-NEXT: [6]: HasSideEffects (U)30 31# CHECK: [1] [2] [3] [4] [5] [6] Instructions:32# CHECK-NEXT: 3 2 1.00 * U stmxcsr -4(%rsp)33# CHECK-NEXT: 1 1 0.25 movl $-24577, %eax34# CHECK-NEXT: 2 6 0.50 * andl -4(%rsp), %eax35# CHECK-NEXT: 1 1 1.00 * movl %eax, -8(%rsp)36# CHECK-NEXT: 3 7 1.00 * * U ldmxcsr -8(%rsp)37# CHECK-NEXT: 3 7 1.00 U retq38 39# CHECK: Resources:40# CHECK-NEXT: [0] - HWDivider41# CHECK-NEXT: [1] - HWFPDivider42# CHECK-NEXT: [2] - HWPort043# CHECK-NEXT: [3] - HWPort144# CHECK-NEXT: [4] - HWPort245# CHECK-NEXT: [5] - HWPort346# CHECK-NEXT: [6] - HWPort447# CHECK-NEXT: [7] - HWPort548# CHECK-NEXT: [8] - HWPort649# CHECK-NEXT: [9] - HWPort750 51# CHECK: Resource pressure per iteration:52# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]53# CHECK-NEXT: - - 1.77 1.71 1.75 1.75 2.00 1.81 1.71 1.5054 55# CHECK: Resource pressure by instruction:56# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:57# CHECK-NEXT: - - - - - - 1.00 1.00 - 1.00 stmxcsr -4(%rsp)58# CHECK-NEXT: - - 0.26 0.46 - - - 0.27 0.01 - movl $-24577, %eax59# CHECK-NEXT: - - 0.28 0.28 0.49 0.51 - 0.07 0.37 - andl -4(%rsp), %eax60# CHECK-NEXT: - - - - 0.18 0.32 1.00 - - 0.50 movl %eax, -8(%rsp)61# CHECK-NEXT: - - 1.00 0.67 0.58 0.42 - - 0.33 - ldmxcsr -8(%rsp)62# CHECK-NEXT: - - 0.23 0.30 0.50 0.50 - 0.47 1.00 - retq63 64# CHECK: Timeline view:65# CHECK-NEXT: 0123456789 01266# CHECK-NEXT: Index 0123456789 012345678967 68# CHECK: [0,0] DeeER. . . . . . . stmxcsr -4(%rsp)69# CHECK-NEXT: [0,1] DeE-R. . . . . . . movl $-24577, %eax70# CHECK-NEXT: [0,2] .DeeeeeeER. . . . . . andl -4(%rsp), %eax71# CHECK-NEXT: [0,3] .D======eER . . . . . movl %eax, -8(%rsp)72# CHECK-NEXT: [0,4] . D=====eeeeeeeER . . . . ldmxcsr -8(%rsp)73# CHECK-NEXT: [0,5] . DeeeeeeeE----R . . . . retq74# CHECK-NEXT: [1,0] . D==========eeER . . . . stmxcsr -4(%rsp)75# CHECK-NEXT: [1,1] . DeE-----------R . . . . movl $-24577, %eax76# CHECK-NEXT: [1,2] . DeeeeeeE-----R . . . . andl -4(%rsp), %eax77# CHECK-NEXT: [1,3] . D==========eER . . . . movl %eax, -8(%rsp)78# CHECK-NEXT: [1,4] . .D=========eeeeeeeER. . . ldmxcsr -8(%rsp)79# CHECK-NEXT: [1,5] . . D=eeeeeeeE-------R. . . retq80# CHECK-NEXT: [2,0] . . D==============eeER . . stmxcsr -4(%rsp)81# CHECK-NEXT: [2,1] . . DeE---------------R . . movl $-24577, %eax82# CHECK-NEXT: [2,2] . . DeeeeeeE---------R . . andl -4(%rsp), %eax83# CHECK-NEXT: [2,3] . . D==============eER . . movl %eax, -8(%rsp)84# CHECK-NEXT: [2,4] . . D=============eeeeeeeER ldmxcsr -8(%rsp)85# CHECK-NEXT: [2,5] . . .DeeeeeeeE------------R retq86 87# CHECK: Average Wait times (based on the timeline view):88# CHECK-NEXT: [0]: Executions89# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue90# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready91# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage92 93# CHECK: [0] [1] [2] [3]94# CHECK-NEXT: 0. 3 9.0 0.3 0.0 stmxcsr -4(%rsp)95# CHECK-NEXT: 1. 3 1.0 1.0 9.0 movl $-24577, %eax96# CHECK-NEXT: 2. 3 1.0 1.0 4.7 andl -4(%rsp), %eax97# CHECK-NEXT: 3. 3 11.0 0.7 0.0 movl %eax, -8(%rsp)98# CHECK-NEXT: 4. 3 10.0 0.0 0.0 ldmxcsr -8(%rsp)99# CHECK-NEXT: 5. 3 1.3 1.3 7.7 retq100# CHECK-NEXT: 3 5.6 0.7 3.6 <total>101