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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s3 4# An instruction that writes to a 32-bit register will not have any false5# dependence on the corresponding 64-bit register because the upper part of6# the 64-bit register is set to zero7 8imulq %rax, %rcx9addl %edx, %ecx10addq %rcx, %rdx11 12# CHECK: Iterations: 113# CHECK-NEXT: Instructions: 314# CHECK-NEXT: Total Cycles: 815# CHECK-NEXT: Total uOps: 316 17# CHECK: Dispatch Width: 618# CHECK-NEXT: uOps Per Cycle: 0.3819# CHECK-NEXT: IPC: 0.3820# CHECK-NEXT: Block RThroughput: 1.021 22# CHECK: Instruction Info:23# CHECK-NEXT: [1]: #uOps24# CHECK-NEXT: [2]: Latency25# CHECK-NEXT: [3]: RThroughput26# CHECK-NEXT: [4]: MayLoad27# CHECK-NEXT: [5]: MayStore28# CHECK-NEXT: [6]: HasSideEffects (U)29 30# CHECK: [1] [2] [3] [4] [5] [6] Instructions:31# CHECK-NEXT: 1 3 1.00 imulq %rax, %rcx32# CHECK-NEXT: 1 1 0.25 addl %edx, %ecx33# CHECK-NEXT: 1 1 0.25 addq %rcx, %rdx34 35# CHECK: Timeline view:36# CHECK-NEXT: Index 0123456737 38# CHECK: [0,0] DeeeER . imulq %rax, %rcx39# CHECK-NEXT: [0,1] D===eER. addl %edx, %ecx40# CHECK-NEXT: [0,2] D====eER addq %rcx, %rdx41 42# CHECK: Average Wait times (based on the timeline view):43# CHECK-NEXT: [0]: Executions44# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue45# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready46# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage47 48# CHECK: [0] [1] [2] [3]49# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rcx50# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addl %edx, %ecx51# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addq %rcx, %rdx52# CHECK-NEXT: 1 3.3 0.3 0.0 <total>53