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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULLREPORT3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=true < %s | FileCheck %s -check-prefixes=ALL,FULLREPORT4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=false < %s | FileCheck %s -check-prefix=ALL5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=ALL6 7add %eax, %eax8 9# ALL: Iterations: 10010# ALL-NEXT: Instructions: 10011# ALL-NEXT: Total Cycles: 10312# ALL-NEXT: Total uOps: 10013 14# ALL: Dispatch Width: 215# ALL-NEXT: uOps Per Cycle: 0.9716# ALL-NEXT: IPC: 0.9717# ALL-NEXT: Block RThroughput: 0.518 19# ALL: Instruction Info:20# ALL-NEXT: [1]: #uOps21# ALL-NEXT: [2]: Latency22# ALL-NEXT: [3]: RThroughput23# ALL-NEXT: [4]: MayLoad24# ALL-NEXT: [5]: MayStore25# ALL-NEXT: [6]: HasSideEffects (U)26 27# ALL: [1] [2] [3] [4] [5] [6] Instructions:28# ALL-NEXT: 1 1 0.50 addl %eax, %eax29 30# FULLREPORT: Dynamic Dispatch Stall Cycles:31# FULLREPORT-NEXT: RAT - Register unavailable: 032# FULLREPORT-NEXT: RCU - Retire tokens unavailable: 033# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 (59.2%)34# FULLREPORT-NEXT: LQ - Load queue full: 035# FULLREPORT-NEXT: SQ - Store queue full: 036# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 037# FULLREPORT-NEXT: USH - Uncategorised Structural Hazard: 038 39# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:40# FULLREPORT-NEXT: [# dispatched], [# cycles]41# FULLREPORT-NEXT: 0, 22 (21.4%)42# FULLREPORT-NEXT: 1, 62 (60.2%)43# FULLREPORT-NEXT: 2, 19 (18.4%)44 45# FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:46# FULLREPORT-NEXT: [# issued], [# cycles]47# FULLREPORT-NEXT: 0, 3 (2.9%)48# FULLREPORT-NEXT: 1, 100 (97.1%)49 50# FULLREPORT: Scheduler's queue usage:51# FULLREPORT-NEXT: [1] Resource name.52# FULLREPORT-NEXT: [2] Average number of used buffer entries.53# FULLREPORT-NEXT: [3] Maximum number of used buffer entries.54# FULLREPORT-NEXT: [4] Total number of buffer entries.55 56# FULLREPORT: [1] [2] [3] [4]57# FULLREPORT-NEXT: JALU01 15 20 2058# FULLREPORT-NEXT: JFPU01 0 0 1859# FULLREPORT-NEXT: JLSAGU 0 0 1260 61# FULLREPORT: Retire Control Unit - number of cycles where we saw N instructions retired:62# FULLREPORT-NEXT: [# retired], [# cycles]63# FULLREPORT-NEXT: 0, 3 (2.9%)64# FULLREPORT-NEXT: 1, 100 (97.1%)65 66# FULLREPORT: Total ROB Entries: 6467# FULLREPORT-NEXT: Max Used ROB Entries: 22 ( 34.4% )68# FULLREPORT-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% )69 70# FULLREPORT: Register File statistics:71# FULLREPORT-NEXT: Total number of mappings created: 20072# FULLREPORT-NEXT: Max number of mappings used: 4473 74# FULLREPORT: * Register File #1 -- JFpuPRF:75# FULLREPORT-NEXT: Number of physical registers: 7276# FULLREPORT-NEXT: Total number of mappings created: 077# FULLREPORT-NEXT: Max number of mappings used: 078 79# FULLREPORT: * Register File #2 -- JIntegerPRF:80# FULLREPORT-NEXT: Number of physical registers: 6481# FULLREPORT-NEXT: Total number of mappings created: 20082# FULLREPORT-NEXT: Max number of mappings used: 4483 84# ALL: Resources:85# ALL-NEXT: [0] - JALU086# ALL-NEXT: [1] - JALU187# ALL-NEXT: [2] - JDiv88# ALL-NEXT: [3] - JFPA89# ALL-NEXT: [4] - JFPM90# ALL-NEXT: [5] - JFPU091# ALL-NEXT: [6] - JFPU192# ALL-NEXT: [7] - JLAGU93# ALL-NEXT: [8] - JMul94# ALL-NEXT: [9] - JSAGU95# ALL-NEXT: [10] - JSTC96# ALL-NEXT: [11] - JVALU097# ALL-NEXT: [12] - JVALU198# ALL-NEXT: [13] - JVIMUL99 100# ALL: Resource pressure per iteration:101# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]102# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - -103 104# ALL: Resource pressure by instruction:105# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:106# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax107