108 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefixes=ALL,FULL5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL6# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL7 8add %eax, %eax9 10# ALL: Iterations: 10011# ALL-NEXT: Instructions: 10012# ALL-NEXT: Total Cycles: 10313# ALL-NEXT: Total uOps: 10014 15# ALL: Dispatch Width: 216# ALL-NEXT: uOps Per Cycle: 0.9717# ALL-NEXT: IPC: 0.9718# ALL-NEXT: Block RThroughput: 0.519 20# ALL: Instruction Info:21# ALL-NEXT: [1]: #uOps22# ALL-NEXT: [2]: Latency23# ALL-NEXT: [3]: RThroughput24# ALL-NEXT: [4]: MayLoad25# ALL-NEXT: [5]: MayStore26# ALL-NEXT: [6]: HasSideEffects (U)27 28# ALL: [1] [2] [3] [4] [5] [6] Instructions:29# ALL-NEXT: 1 1 0.50 addl %eax, %eax30 31# FULL: Dynamic Dispatch Stall Cycles:32# FULL-NEXT: RAT - Register unavailable: 033# FULL-NEXT: RCU - Retire tokens unavailable: 034# FULL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%)35# FULL-NEXT: LQ - Load queue full: 036# FULL-NEXT: SQ - Store queue full: 037# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 038# FULL-NEXT: USH - Uncategorised Structural Hazard: 039 40# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:41# FULL-NEXT: [# dispatched], [# cycles]42# FULL-NEXT: 0, 22 (21.4%)43# FULL-NEXT: 1, 62 (60.2%)44# FULL-NEXT: 2, 19 (18.4%)45 46# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:47# ALL-NEXT: [# issued], [# cycles]48# ALL-NEXT: 0, 3 (2.9%)49# ALL-NEXT: 1, 100 (97.1%)50 51# ALL: Scheduler's queue usage:52# ALL-NEXT: [1] Resource name.53# ALL-NEXT: [2] Average number of used buffer entries.54# ALL-NEXT: [3] Maximum number of used buffer entries.55# ALL-NEXT: [4] Total number of buffer entries.56 57# ALL: [1] [2] [3] [4]58# ALL-NEXT: JALU01 15 20 2059# ALL-NEXT: JFPU01 0 0 1860# ALL-NEXT: JLSAGU 0 0 1261 62# ALL: Retire Control Unit - number of cycles where we saw N instructions retired:63# ALL-NEXT: [# retired], [# cycles]64# ALL-NEXT: 0, 3 (2.9%)65# ALL-NEXT: 1, 100 (97.1%)66 67# ALL: Total ROB Entries: 6468# ALL-NEXT: Max Used ROB Entries: 22 ( 34.4% )69# ALL-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% )70 71# ALL: Register File statistics:72# ALL-NEXT: Total number of mappings created: 20073# ALL-NEXT: Max number of mappings used: 4474 75# ALL: * Register File #1 -- JFpuPRF:76# ALL-NEXT: Number of physical registers: 7277# ALL-NEXT: Total number of mappings created: 078# ALL-NEXT: Max number of mappings used: 079 80# ALL: * Register File #2 -- JIntegerPRF:81# ALL-NEXT: Number of physical registers: 6482# ALL-NEXT: Total number of mappings created: 20083# ALL-NEXT: Max number of mappings used: 4484 85# ALL: Resources:86# ALL-NEXT: [0] - JALU087# ALL-NEXT: [1] - JALU188# ALL-NEXT: [2] - JDiv89# ALL-NEXT: [3] - JFPA90# ALL-NEXT: [4] - JFPM91# ALL-NEXT: [5] - JFPU092# ALL-NEXT: [6] - JFPU193# ALL-NEXT: [7] - JLAGU94# ALL-NEXT: [8] - JMul95# ALL-NEXT: [9] - JSAGU96# ALL-NEXT: [10] - JSTC97# ALL-NEXT: [11] - JVALU098# ALL-NEXT: [12] - JVALU199# ALL-NEXT: [13] - JVIMUL100 101# ALL: Resource pressure per iteration:102# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]103# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - -104 105# ALL: Resource pressure by instruction:106# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:107# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax108