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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-13# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-24# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=3 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-35# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-46# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-DEC-27 8# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-19# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-210# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-DEC-111 12add %eax, %eax13add %ebx, %ebx14add %ecx, %ecx15add %edx, %edx16 17# BTVER2-DEC-2: Iterations: 150018# BTVER2-DEC-2-NEXT: Instructions: 600019# BTVER2-DEC-2-NEXT: Total Cycles: 300320# BTVER2-DEC-2-NEXT: Total uOps: 600021 22# BTVER2-DEC-2: Dispatch Width: 223# BTVER2-DEC-2-NEXT: uOps Per Cycle: 2.0024# BTVER2-DEC-2-NEXT: IPC: 2.0025# BTVER2-DEC-2-NEXT: Block RThroughput: 2.026 27# BTVER2-DEC-1: Iterations: 150028# BTVER2-DEC-1-NEXT: Instructions: 600029# BTVER2-DEC-1-NEXT: Total Cycles: 600330# BTVER2-DEC-1-NEXT: Total uOps: 600031 32# BTVER2-UOPQ-1: Iterations: 150033# BTVER2-UOPQ-1-NEXT: Instructions: 600034# BTVER2-UOPQ-1-NEXT: Total Cycles: 600335# BTVER2-UOPQ-1-NEXT: Total uOps: 600036 37# BTVER2-UOPQ-2: Iterations: 150038# BTVER2-UOPQ-2-NEXT: Instructions: 600039# BTVER2-UOPQ-2-NEXT: Total Cycles: 300340# BTVER2-UOPQ-2-NEXT: Total uOps: 600041 42# HASWELL-DEC-2: Iterations: 150043# HASWELL-DEC-2-NEXT: Instructions: 600044# HASWELL-DEC-2-NEXT: Total Cycles: 300345# HASWELL-DEC-2-NEXT: Total uOps: 600046 47# HASWELL-UOPQ-1: Iterations: 150048# HASWELL-UOPQ-1-NEXT: Instructions: 600049# HASWELL-UOPQ-1-NEXT: Total Cycles: 600350# HASWELL-UOPQ-1-NEXT: Total uOps: 600051 52# HASWELL-UOPQ-2: Iterations: 150053# HASWELL-UOPQ-2-NEXT: Instructions: 600054# HASWELL-UOPQ-2-NEXT: Total Cycles: 300355# HASWELL-UOPQ-2-NEXT: Total uOps: 600056 57# HASWELL-UOPQ-3: Iterations: 150058# HASWELL-UOPQ-3-NEXT: Instructions: 600059# HASWELL-UOPQ-3-NEXT: Total Cycles: 200360# HASWELL-UOPQ-3-NEXT: Total uOps: 600061 62# HASWELL-UOPQ-4: Iterations: 150063# HASWELL-UOPQ-4-NEXT: Instructions: 600064# HASWELL-UOPQ-4-NEXT: Total Cycles: 150365# HASWELL-UOPQ-4-NEXT: Total uOps: 600066 67# BTVER2-DEC-1: Dispatch Width: 268# BTVER2-DEC-1-NEXT: uOps Per Cycle: 1.0069# BTVER2-DEC-1-NEXT: IPC: 1.0070# BTVER2-DEC-1-NEXT: Block RThroughput: 2.071 72# BTVER2-UOPQ-1: Dispatch Width: 273# BTVER2-UOPQ-1-NEXT: uOps Per Cycle: 1.0074# BTVER2-UOPQ-1-NEXT: IPC: 1.0075# BTVER2-UOPQ-1-NEXT: Block RThroughput: 2.076 77# BTVER2-UOPQ-2: Dispatch Width: 278# BTVER2-UOPQ-2-NEXT: uOps Per Cycle: 2.0079# BTVER2-UOPQ-2-NEXT: IPC: 2.0080# BTVER2-UOPQ-2-NEXT: Block RThroughput: 2.081 82# HASWELL-DEC-2: Dispatch Width: 483# HASWELL-DEC-2-NEXT: uOps Per Cycle: 2.0084# HASWELL-DEC-2-NEXT: IPC: 2.0085# HASWELL-DEC-2-NEXT: Block RThroughput: 1.086 87# HASWELL-UOPQ-1: Dispatch Width: 488# HASWELL-UOPQ-1-NEXT: uOps Per Cycle: 1.0089# HASWELL-UOPQ-1-NEXT: IPC: 1.0090# HASWELL-UOPQ-1-NEXT: Block RThroughput: 1.091 92# HASWELL-UOPQ-2: Dispatch Width: 493# HASWELL-UOPQ-2-NEXT: uOps Per Cycle: 2.0094# HASWELL-UOPQ-2-NEXT: IPC: 2.0095# HASWELL-UOPQ-2-NEXT: Block RThroughput: 1.096 97# HASWELL-UOPQ-3: Dispatch Width: 498# HASWELL-UOPQ-3-NEXT: uOps Per Cycle: 3.0099# HASWELL-UOPQ-3-NEXT: IPC: 3.00100# HASWELL-UOPQ-3-NEXT: Block RThroughput: 1.0101 102# HASWELL-UOPQ-4: Dispatch Width: 4103# HASWELL-UOPQ-4-NEXT: uOps Per Cycle: 3.99104# HASWELL-UOPQ-4-NEXT: IPC: 3.99105# HASWELL-UOPQ-4-NEXT: Block RThroughput: 1.0106