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1@RUN: llvm-mc -triple arm-none-eabi -mcpu=cortex-m33 -filetype=obj %s | llvm-objdump -d --mcpu=cortex-m3 - | FileCheck %s2 3@ Check that instructions that are disassembled as <undefined> within an IT4@ block advance the IT state. This prevents the IT state spilling over into5@ the next instruction.6 7@ The vldmiaeq instruction is disassembled as <undefined> with8@ -mcpu=cortex-m3 as this does not have a fpu.9.text10.fpu fp-armv811.thumb12 ite eq13 vldmiaeq r0!, {s16-s31}14 addne r0, r0, r015 add r1, r1, r116 17 itet eq18 vldmiaeq r0!, {s16-s31}19 vldmiane r0!, {s16-s31}20 vldmiaeq r0!, {s16-s31}21 add r0, r0, r022 add r1, r1, r123 add r2, r2, r224 25 it eq26 vldmiaeq r0!, {s16-s31}27 28 it ne29 addne r0, r0, r030 31@ CHECK: 0: bf0c ite eq32@ CHECK-NEXT: 2: ecb0 8a10 <unknown>33@ CHECK-NEXT: 6: 1800 addne r0, r0, r034@ CHECK-NEXT: 8: 4409 add r1, r135@ CHECK-NEXT: a: bf0a itet eq36@ CHECK-NEXT: c: ecb0 8a10 <unknown>37@ CHECK-NEXT: 10: ecb0 8a10 <unknown>38@ CHECK-NEXT: 14: ecb0 8a10 <unknown>39@ CHECK-NEXT: 18: 4400 add r0, r040@ CHECK-NEXT: 1a: 4409 add r1, r141@ CHECK-NEXT: 1c: 4412 add r2, r242@ CHECK-NEXT: 1e: bf08 it eq43@ CHECK-NEXT: 20: ecb0 8a10 <unknown>44@ CHECK-NEXT: 24: bf18 it ne45@ CHECK-NEXT: 26: 1800 addne r0, r0, r046