191 lines · plain
1# REQUIRES: amdgpu-registered-target2# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-defs -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefixes=CHECK-INTERESTINGNESS0,ALL --test-arg %s --test-arg --input-file %s -o %t 2> %t.log3# RUN: FileCheck --match-full-lines --check-prefixes=RESULT0,ALL %s < %t4 5# ALL-LABEL: name: func06# CHECK-INTERESTINGNESS0: V_MUL_F327 8# RESULT0: %mul1:vgpr_32 = IMPLICIT_DEF9# RESULT0-NOT: V_ADD_CO_U3210# RESULT0: %addco0:vgpr_32 = IMPLICIT_DEF11# RESULT0-NEXT: %addco1:sreg_64_xexec = IMPLICIT_DEF12# RESULT0-NOT: V_ADD_CO_U3213 14---15name: func016tracksRegLiveness: true17body: |18 bb.0:19 liveins: $vgpr0, $vgpr120 21 S_WAITCNT 022 %vgpr0:vgpr_32 = COPY $vgpr023 %vgpr1:vgpr_32 = COPY $vgpr124 %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec25 %mul1:vgpr_32 = V_MUL_F32_e32 %vgpr1, %vgpr0, implicit $mode, implicit $exec26 %addco0:vgpr_32, %addco1:sreg_64_xexec = V_ADD_CO_U32_e64 %vgpr0, %vgpr1, 0, implicit $exec27 S_NOP 0, implicit %addco028 S_NOP 0, implicit %addco129 S_ENDPGM 0, implicit %mul0, implicit %mul130...31 32# ALL-LABEL: name: subreg_def33# CHECK-INTERESTINGNESS0: %super.sub034 35# RESULT0: undef %super.sub0:vreg_64 = IMPLICIT_DEF36# RESULT0-NEXT: %super.sub1:vreg_64 = IMPLICIT_DEF37---38name: subreg_def39tracksRegLiveness: true40body: |41 bb.0:42 liveins: $vgpr0, $vgpr143 44 %vgpr0:vgpr_32 = COPY $vgpr045 %vgpr1:vgpr_32 = COPY $vgpr146 undef %super.sub0:vreg_64 = IMPLICIT_DEF47 %super.sub1:vreg_64 = V_ADD_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec48 49 S_NOP 0, implicit %super.sub050 S_ENDPGM 0, implicit %super.sub051...52 53# Make sure we don't introduce multiple implicit_defs if an54# instruction has repeated, identical defs.55# ALL-LABEL: name: multi_def56# CHECK-INTERESTINGNESS0: S_NOP 257 58# RESULT0: %redef:vgpr_32 = IMPLICIT_DEF59# RESULT0-NOT: %redef:vgpr_32 = IMPLICIT_DEF60---61name: multi_def62tracksRegLiveness: true63body: |64 bb.0:65 liveins: $vgpr0, $vgpr166 67 %vgpr0:vgpr_32 = COPY $vgpr068 %vgpr1:vgpr_32 = COPY $vgpr169 S_NOP 1, implicit-def %redef:vgpr_32, implicit-def %redef:vgpr_3270 S_NOP 2, implicit %redef71...72 73# ALL-LABEL: name: multi_def_keep_two74# CHECK-INTERESTINGNESS0: implicit-def %def075# CHECK-INTERESTINGNESS0: implicit-def %def276 77# RESULT0: %def1:vgpr_32 = IMPLICIT_DEF78# RESULT0-NEXT: S_NOP 1, implicit-def %def0, implicit-def %def279# RESULT0-NEXT: S_NOP 2, implicit %def0, implicit %def1, implicit %def280 81---82name: multi_def_keep_two83tracksRegLiveness: true84body: |85 bb.0:86 liveins: $vgpr0, $vgpr187 88 %vgpr0:vgpr_32 = COPY $vgpr089 %vgpr1:vgpr_32 = COPY $vgpr190 S_NOP 1, implicit-def %def0:vgpr_32, implicit-def %def1:vgpr_32, implicit-def %def2:vgpr_3291 S_NOP 2, implicit %def0, implicit %def1, implicit %def292...93 94# ALL-LABEL: name: multi_def_subreg95# CHECK-INTERESTINGNESS0: S_NOP 496 97# RESULT0: undef %redef.sub0:vreg_64 = IMPLICIT_DEF98# RESULT0: undef %redef.sub1:vreg_64 = IMPLICIT_DEF99---100name: multi_def_subreg101tracksRegLiveness: true102body: |103 bb.0:104 liveins: $vgpr0, $vgpr1105 106 %vgpr0:vgpr_32 = COPY $vgpr0107 %vgpr1:vgpr_32 = COPY $vgpr1108 S_NOP 3, undef implicit-def %redef.sub0:vreg_64, undef implicit-def %redef.sub1:vreg_64109 S_NOP 4, implicit %redef110...111 112# ALL-LABEL: name: multi_def_subreg_same_subreg113# CHECK-INTERESTINGNESS0: S_NOP 4114 115# RESULT0-NOT: implicit-def %redef116# RESULT0: undef %redef.sub0:vreg_64 = IMPLICIT_DEF117# RESULT0-NOT: implicit-def %redef118---119name: multi_def_subreg_same_subreg120tracksRegLiveness: true121body: |122 bb.0:123 liveins: $vgpr0, $vgpr1124 125 %vgpr0:vgpr_32 = COPY $vgpr0126 %vgpr1:vgpr_32 = COPY $vgpr1127 S_NOP 3, undef implicit-def %redef.sub0:vreg_64, undef implicit-def %redef.sub0:vreg_64128 S_NOP 4, implicit %redef129...130 131# ALL-LABEL: name: tied_def132# CHECK-INTERESTINGNESS0: V_MAC_F32133 134# RESULT0: %mac0:vgpr_32 = V_MAC_F32_e32 %vgpr0, %vgpr1, undef %mac0, implicit $mode, implicit $exec135# RESULT0: %mac1:vgpr_32 = IMPLICIT_DEF136---137name: tied_def138tracksRegLiveness: true139body: |140 bb.0:141 liveins: $vgpr0, $vgpr1142 143 S_WAITCNT 0144 %vgpr0:vgpr_32 = COPY $vgpr0145 %vgpr1:vgpr_32 = COPY $vgpr1146 %mac0:vgpr_32 = V_MAC_F32_e32 %vgpr0, %vgpr1, undef %mac0, implicit $mode, implicit $exec147 %mac1:vgpr_32 = V_MAC_F32_e32 %vgpr1, %vgpr0, %mac0, implicit $mode, implicit $exec148 S_ENDPGM 0, implicit %mac0, implicit %mac1149...150 151# ALL-LABEL: name: generic_reg152# CHECK-INTERESTINGNESS0: %fmul:vgpr(s32) =153# RESULT0: %fmul:vgpr(s32) = G_IMPLICIT_DEF154---155name: generic_reg156tracksRegLiveness: true157body: |158 bb.0:159 liveins: $vgpr0, $vgpr1160 161 %vgpr0:vgpr_32(s32) = COPY $vgpr0162 %vgpr1:vgpr_32(s32) = COPY $vgpr1163 %fmul:vgpr(s32) = G_FMUL %vgpr0, %vgpr1164 S_ENDPGM 0, implicit %fmul165...166 167# ALL-LABEL: name: terminator_def168 169# CHECK-INTERESTINGNESS0: %exec_copy0:sreg_64_xexec = S_MOV_B64_term $exec170 171# RESULT0: %exec_copy0:sreg_64_xexec = S_MOV_B64_term $exec172# RESULT0-NEXT: %exec_copy1:sreg_64_xexec = S_MOV_B64_term $exec173# RESULT0-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec174---175name: terminator_def176tracksRegLiveness: true177body: |178 bb.0:179 liveins: $sgpr8_sgpr9180 181 %exec_copy0:sreg_64_xexec = S_MOV_B64_term $exec182 %exec_copy1:sreg_64_xexec = S_MOV_B64_term $exec183 S_CBRANCH_EXECZ %bb.2, implicit $exec184 185 bb.1:186 S_NOP 7187 188 bb.2:189 S_ENDPGM 0, implicit %exec_copy0, implicit %exec_copy1190...191