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1# REQUIRES: amdgpu-registered-target2# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log3# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t4 5# CHECK-INTERESTINGNESS: V_MUL_F32_e32 %vgpr06# CHECK-INTERESTINGNESS: V_MUL_F32_e32 {{.*}}%vgpr1, %vgpr07 8# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr09# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr310 11 12# RESULT: %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, undef %vgpr1, implicit $mode, implicit $exec13# RESULT: %mul1:vgpr_32 = V_MUL_F32_e32 undef %vgpr1, %vgpr0, implicit $mode, implicit $exec14# RESULT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec15# RESULT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec16# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr017# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr318# RESULT: %impdef:vreg_64 = IMPLICIT_DEF19# RESULT: GLOBAL_STORE_DWORD undef %ptr, undef %impdef.sub1, 0, 0, implicit $exec20# RESULT: undef %impdef.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec21# RESULT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc22# RESULT: S_BARRIER23# RESULT: S_ENDPGM 024 25--- |26 define void @func() {27 ret void28 }29 30 declare void @callee()31...32 33---34name: func35tracksRegLiveness: true36body: |37 bb.0:38 liveins: $vgpr0, $vgpr139 40 S_WAITCNT 041 %vgpr0:vgpr_32 = COPY $vgpr042 %vgpr1:vgpr_32 = COPY $vgpr143 %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec44 %mul1:vgpr_32 = V_MUL_F32_e32 %vgpr1, %vgpr0, implicit $mode, implicit $exec45 %call_target:sreg_64 = IMPLICIT_DEF46 $vgpr0 = V_MOV_B32_e32 0, implicit $exec47 $vgpr1 = V_MOV_B32_e32 1, implicit $exec48 $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr0, implicit $vgpr149 $vgpr2 = V_MOV_B32_e32 2, implicit $exec50 $vgpr3 = V_MOV_B32_e32 3, implicit $exec51 $sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr2, implicit $vgpr352 %impdef:vreg_64 = IMPLICIT_DEF53 %ptr:vreg_64 = IMPLICIT_DEF54 GLOBAL_STORE_DWORD %ptr, %impdef.sub1, 0, 0, implicit $exec55 %impdef.sub0 = V_MOV_B32_e32 0, implicit $exec56 $scc = IMPLICIT_DEF57 S_CBRANCH_SCC1 %bb.1, implicit $scc58 59 bb.1:60 S_BARRIER61 S_ENDPGM 0, implicit %mul0, implicit %mul162...63 64