2153 lines · cpp
1//===- KnownBitsTest.cpp -------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "GISelMITest.h"10#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"11#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"12 13// Check that we are able to track bits through PHIs14// and get the intersections of everything we know on each operand.15TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) {16 StringRef MIRString = " bb.10:\n"17 " %10:_(s8) = G_CONSTANT i8 3\n"18 " %11:_(s1) = G_IMPLICIT_DEF\n"19 " G_BRCOND %11(s1), %bb.11\n"20 " G_BR %bb.12\n"21 "\n"22 " bb.11:\n"23 " %12:_(s8) = G_CONSTANT i8 2\n"24 " G_BR %bb.12\n"25 "\n"26 " bb.12:\n"27 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n"28 " %14:_(s8) = COPY %13\n";29 setUp(MIRString);30 if (!TM)31 GTEST_SKIP();32 Register CopyReg = Copies[Copies.size() - 1];33 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);34 Register SrcReg = FinalCopy->getOperand(1).getReg();35 Register DstReg = FinalCopy->getOperand(0).getReg();36 GISelValueTracking Info(*MF);37 KnownBits Res = Info.getKnownBits(SrcReg);38 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());39 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());40 41 KnownBits Res2 = Info.getKnownBits(DstReg);42 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());43 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());44}45 46// Check that we report we know nothing when we hit a47// non-generic register.48// Note: this could be improved though!49TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIToNonGenericReg) {50 StringRef MIRString = " bb.10:\n"51 " %10:gpr32 = MOVi32imm 3\n"52 " %11:_(s1) = G_IMPLICIT_DEF\n"53 " G_BRCOND %11(s1), %bb.11\n"54 " G_BR %bb.12\n"55 "\n"56 " bb.11:\n"57 " %12:_(s8) = G_CONSTANT i8 2\n"58 " G_BR %bb.12\n"59 "\n"60 " bb.12:\n"61 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n"62 " %14:_(s8) = COPY %13\n";63 setUp(MIRString);64 if (!TM)65 GTEST_SKIP();66 Register CopyReg = Copies[Copies.size() - 1];67 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);68 Register SrcReg = FinalCopy->getOperand(1).getReg();69 Register DstReg = FinalCopy->getOperand(0).getReg();70 GISelValueTracking Info(*MF);71 KnownBits Res = Info.getKnownBits(SrcReg);72 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());73 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());74 75 KnownBits Res2 = Info.getKnownBits(DstReg);76 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());77 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());78}79 80// Check that we know nothing when at least one value of a PHI81// comes from something we cannot analysis.82// This test is not particularly interesting, it is just83// here to cover the code that stops the analysis of PHIs84// earlier. In that case, we would not even look at the85// second incoming value.86TEST_F(AArch64GISelMITest, TestKnownBitsUnknownPHI) {87 StringRef MIRString =88 " bb.10:\n"89 " %10:_(s64) = COPY %0\n"90 " %11:_(s1) = G_IMPLICIT_DEF\n"91 " G_BRCOND %11(s1), %bb.11\n"92 " G_BR %bb.12\n"93 "\n"94 " bb.11:\n"95 " %12:_(s64) = G_CONSTANT i64 2\n"96 " G_BR %bb.12\n"97 "\n"98 " bb.12:\n"99 " %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n"100 " %14:_(s64) = COPY %13\n";101 setUp(MIRString);102 if (!TM)103 GTEST_SKIP();104 Register CopyReg = Copies[Copies.size() - 1];105 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);106 Register SrcReg = FinalCopy->getOperand(1).getReg();107 Register DstReg = FinalCopy->getOperand(0).getReg();108 GISelValueTracking Info(*MF);109 KnownBits Res = Info.getKnownBits(SrcReg);110 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());111 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());112 113 KnownBits Res2 = Info.getKnownBits(DstReg);114 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());115 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());116}117 118// Check that we manage to process PHIs that loop on themselves.119// For now, the analysis just stops and assumes it knows nothing,120// eventually we could teach it how to properly track phis that121// loop back.122TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIWithLoop) {123 StringRef MIRString =124 " bb.10:\n"125 " %10:_(s8) = G_CONSTANT i8 3\n"126 " %11:_(s1) = G_IMPLICIT_DEF\n"127 " G_BRCOND %11(s1), %bb.11\n"128 " G_BR %bb.12\n"129 "\n"130 " bb.11:\n"131 " %12:_(s8) = G_CONSTANT i8 2\n"132 " G_BR %bb.12\n"133 "\n"134 " bb.12:\n"135 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n"136 " %14:_(s8) = COPY %13\n"137 " G_BR %bb.12\n";138 setUp(MIRString);139 if (!TM)140 GTEST_SKIP();141 Register CopyReg = Copies[Copies.size() - 1];142 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);143 Register SrcReg = FinalCopy->getOperand(1).getReg();144 Register DstReg = FinalCopy->getOperand(0).getReg();145 GISelValueTracking Info(*MF);146 KnownBits Res = Info.getKnownBits(SrcReg);147 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());148 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());149 150 KnownBits Res2 = Info.getKnownBits(DstReg);151 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());152 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());153}154 155// Check that we don't try to analysis PHIs progression.156// Setting a deep enough max depth would allow to effectively simulate157// what happens in the loop.158// Thus, with a deep enough depth, we could actually figure out159// that %14's zero known bits are actually at least what we know160// for %10, right shifted by one.161// However, this process is super expensive compile-time wise and162// we don't want to reach that conclusion while playing with max depth.163// For now, the analysis just stops and assumes it knows nothing164// on PHIs, but eventually we could teach it how to properly track165// phis that loop back without relying on the luck effect of max166// depth.167TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) {168 StringRef MIRString = " bb.10:\n"169 " %10:_(s8) = G_CONSTANT i8 5\n"170 " %11:_(s8) = G_CONSTANT i8 1\n"171 "\n"172 " bb.12:\n"173 " %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n"174 " %14:_(s8) = G_LSHR %13, %11\n"175 " %15:_(s8) = COPY %14\n"176 " G_BR %bb.12\n";177 setUp(MIRString);178 if (!TM)179 GTEST_SKIP();180 Register CopyReg = Copies[Copies.size() - 1];181 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);182 Register SrcReg = FinalCopy->getOperand(1).getReg();183 Register DstReg = FinalCopy->getOperand(0).getReg();184 GISelValueTracking Info(*MF, /*MaxDepth=*/24);185 KnownBits Res = Info.getKnownBits(SrcReg);186 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());187 // A single iteration on the PHI (%13) gives:188 // %10 has known zero of 0xFA189 // %12 has known zero of 0x80 (we shift right by one so high bit is zero)190 // Therefore, %14's known zero are 0x80 shifted by one 0xC0.191 // If we had simulated the loop we could have more zero bits, basically192 // up to 0xFC (count leading zero of 5, + 1).193 EXPECT_EQ((uint64_t)0xFC, Res.Zero.getZExtValue());194 195 KnownBits Res2 = Info.getKnownBits(DstReg);196 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());197 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());198}199 200TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) {201 StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"202 " %4:_(p0) = G_INTTOPTR %3\n"203 " %5:_(s32) = G_PTRTOINT %4\n"204 " %6:_(s32) = COPY %5\n";205 setUp(MIRString);206 if (!TM)207 GTEST_SKIP();208 unsigned CopyReg = Copies[Copies.size() - 1];209 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);210 unsigned SrcReg = FinalCopy->getOperand(1).getReg();211 GISelValueTracking Info(*MF);212 KnownBits Res = Info.getKnownBits(SrcReg);213 EXPECT_EQ(256u, Res.One.getZExtValue());214 EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());215}216 217TEST_F(AArch64GISelMITest, TestKnownBitsAND) {218 StringRef MIRString = R"(219 %ptr:_(p0) = G_IMPLICIT_DEF220 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))221 %mask0:_(s8) = G_CONSTANT i8 52222 %mask1:_(s8) = G_CONSTANT i8 10223 %tmp0:_(s8) = G_AND %unknown, %mask0224 %val0:_(s8) = G_OR %tmp0, %mask1225 %mask2:_(s8) = G_CONSTANT i8 32226 %mask3:_(s8) = G_CONSTANT i8 24227 %tmp1:_(s8) = G_AND %unknown, %mask2228 %val1:_(s8) = G_OR %tmp1, %mask3229 %and:_(s8) = G_AND %val0, %val1230 %copy_and:_(s8) = COPY %and231)";232 233 setUp(MIRString);234 if (!TM)235 GTEST_SKIP();236 237 Register CopyReg = Copies[Copies.size() - 1];238 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);239 Register SrcReg = FinalCopy->getOperand(1).getReg();240 GISelValueTracking Info(*MF);241 KnownBits Res = Info.getKnownBits(SrcReg);242 // 00??1?10243 // & 00?11000244 // = 00??1000245 EXPECT_EQ(0x08u, Res.One.getZExtValue());246 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());247}248 249TEST_F(AArch64GISelMITest, TestKnownBitsOR) {250 StringRef MIRString = R"(251 %ptr:_(p0) = G_IMPLICIT_DEF252 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))253 %mask0:_(s8) = G_CONSTANT i8 52254 %mask1:_(s8) = G_CONSTANT i8 10255 %tmp0:_(s8) = G_AND %unknown, %mask0256 %val0:_(s8) = G_OR %tmp0, %mask1257 %mask2:_(s8) = G_CONSTANT i8 32258 %mask3:_(s8) = G_CONSTANT i8 24259 %tmp1:_(s8) = G_AND %unknown, %mask2260 %val1:_(s8) = G_OR %tmp1, %mask3261 %or:_(s8) = G_OR %val0, %val1262 %copy_or:_(s8) = COPY %or263)";264 265 setUp(MIRString);266 if (!TM)267 GTEST_SKIP();268 269 Register CopyReg = Copies[Copies.size() - 1];270 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);271 Register SrcReg = FinalCopy->getOperand(1).getReg();272 GISelValueTracking Info(*MF);273 KnownBits Res = Info.getKnownBits(SrcReg);274 // 00??1?10275 // | 00?11000276 // = 00?11?10277 EXPECT_EQ(0x1Au, Res.One.getZExtValue());278 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());279}280 281TEST_F(AArch64GISelMITest, TestKnownBitsXOR) {282 StringRef MIRString = R"(283 %ptr:_(p0) = G_IMPLICIT_DEF284 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))285 %mask0:_(s8) = G_CONSTANT i8 52286 %mask1:_(s8) = G_CONSTANT i8 10287 %tmp0:_(s8) = G_AND %unknown, %mask0288 %val0:_(s8) = G_OR %tmp0, %mask1289 %mask2:_(s8) = G_CONSTANT i8 32290 %mask3:_(s8) = G_CONSTANT i8 24291 %tmp1:_(s8) = G_AND %unknown, %mask2292 %val1:_(s8) = G_OR %tmp1, %mask3293 %xor:_(s8) = G_XOR %val0, %val1294 %copy_xor:_(s8) = COPY %xor295)";296 297 setUp(MIRString);298 if (!TM)299 GTEST_SKIP();300 301 Register CopyReg = Copies[Copies.size() - 1];302 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);303 Register SrcReg = FinalCopy->getOperand(1).getReg();304 GISelValueTracking Info(*MF);305 KnownBits Res = Info.getKnownBits(SrcReg);306 // Xor KnowBits does not track if we are doing xor of unknown bit with itself307 // or negated itself.308 // 00??1?10309 // ^ 00?11000310 // = 00??0?10311 EXPECT_EQ(0x02u, Res.One.getZExtValue());312 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());313}314 315TEST_F(AArch64GISelMITest, TestKnownBitsXORConstant) {316 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n"317 " %4:_(s8) = G_CONSTANT i8 7\n"318 " %5:_(s8) = G_XOR %3, %4\n"319 " %6:_(s8) = COPY %5\n";320 setUp(MIRString);321 if (!TM)322 GTEST_SKIP();323 unsigned CopyReg = Copies[Copies.size() - 1];324 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);325 unsigned SrcReg = FinalCopy->getOperand(1).getReg();326 GISelValueTracking Info(*MF);327 KnownBits Res = Info.getKnownBits(SrcReg);328 EXPECT_EQ(3u, Res.One.getZExtValue());329 EXPECT_EQ(252u, Res.Zero.getZExtValue());330}331 332TEST_F(AArch64GISelMITest, TestKnownBitsASHR) {333 StringRef MIRString = R"(334 %ptr:_(p0) = G_IMPLICIT_DEF335 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))336 %mask0:_(s8) = G_CONSTANT i8 38337 %mask1:_(s8) = G_CONSTANT i8 202338 %tmp0:_(s8) = G_AND %unknown, %mask0339 %val0:_(s8) = G_OR %tmp0, %mask1340 %cst0:_(s8) = G_CONSTANT i8 2341 %ashr0:_(s8) = G_ASHR %val0, %cst0342 %copy_ashr0:_(s8) = COPY %ashr0343 344 %mask2:_(s8) = G_CONSTANT i8 204345 %mask3:_(s8) = G_CONSTANT i8 18346 %tmp1:_(s8) = G_AND %unknown, %mask2347 %val1:_(s8) = G_OR %tmp1, %mask3348 %ashr1:_(s8) = G_ASHR %val1, %cst0349 %copy_ashr1:_(s8) = COPY %ashr1350)";351 352 setUp(MIRString);353 if (!TM)354 GTEST_SKIP();355 356 Register CopyReg0 = Copies[Copies.size() - 2];357 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);358 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();359 GISelValueTracking Info(*MF);360 KnownBits Res0 = Info.getKnownBits(SrcReg0);361 // 11?01??0 >> 2362 // = 1111?01?363 EXPECT_EQ(0xF2u, Res0.One.getZExtValue());364 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());365 366 Register CopyReg1 = Copies[Copies.size() - 1];367 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);368 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();369 KnownBits Res1 = Info.getKnownBits(SrcReg1);370 // ??01??10 >> 2371 // = ????01??372 EXPECT_EQ(0x04u, Res1.One.getZExtValue());373 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());374}375 376TEST_F(AArch64GISelMITest, TestKnownBitsLSHR) {377 StringRef MIRString = R"(378 %ptr:_(p0) = G_IMPLICIT_DEF379 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))380 %mask0:_(s8) = G_CONSTANT i8 38381 %mask1:_(s8) = G_CONSTANT i8 202382 %tmp0:_(s8) = G_AND %unknown, %mask0383 %val0:_(s8) = G_OR %tmp0, %mask1384 %cst0:_(s8) = G_CONSTANT i8 2385 %lshr0:_(s8) = G_LSHR %val0, %cst0386 %copy_lshr0:_(s8) = COPY %lshr0387 388 %mask2:_(s8) = G_CONSTANT i8 204389 %mask3:_(s8) = G_CONSTANT i8 18390 %tmp1:_(s8) = G_AND %unknown, %mask2391 %val1:_(s8) = G_OR %tmp1, %mask3392 %lshr1:_(s8) = G_LSHR %val1, %cst0393 %copy_lshr1:_(s8) = COPY %lshr1394)";395 396 setUp(MIRString);397 if (!TM)398 GTEST_SKIP();399 400 Register CopyReg0 = Copies[Copies.size() - 2];401 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);402 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();403 GISelValueTracking Info(*MF);404 KnownBits Res0 = Info.getKnownBits(SrcReg0);405 // 11?01??0 >> 2406 // = 0011?01?407 EXPECT_EQ(0x32u, Res0.One.getZExtValue());408 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());409 410 Register CopyReg1 = Copies[Copies.size() - 1];411 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);412 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();413 KnownBits Res1 = Info.getKnownBits(SrcReg1);414 // ??01??10 >> 2415 // = 00??01??416 EXPECT_EQ(0x04u, Res1.One.getZExtValue());417 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());418}419 420TEST_F(AArch64GISelMITest, TestKnownBitsSHL) {421 StringRef MIRString = R"(422 %ptr:_(p0) = G_IMPLICIT_DEF423 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))424 %mask0:_(s8) = G_CONSTANT i8 51425 %mask1:_(s8) = G_CONSTANT i8 72426 %tmp:_(s8) = G_AND %unknown, %mask0427 %val:_(s8) = G_OR %tmp, %mask1428 %cst:_(s8) = G_CONSTANT i8 3429 %shl:_(s8) = G_SHL %val, %cst430 %copy_shl:_(s8) = COPY %shl431)";432 433 setUp(MIRString);434 if (!TM)435 GTEST_SKIP();436 437 Register CopyReg = Copies[Copies.size() - 1];438 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);439 Register SrcReg = FinalCopy->getOperand(1).getReg();440 GISelValueTracking Info(*MF);441 KnownBits Res = Info.getKnownBits(SrcReg);442 // 01??10?? << 3443 // = ?10??000444 EXPECT_EQ(0x40u, Res.One.getZExtValue());445 EXPECT_EQ(0x27u, Res.Zero.getZExtValue());446}447 448TEST_F(AArch64GISelMITest, TestKnownBitsADD) {449 StringRef MIRString = R"(450 %ptr:_(p0) = G_IMPLICIT_DEF451 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))452 %mask0:_(s16) = G_CONSTANT i16 4642453 %mask1:_(s16) = G_CONSTANT i16 9536454 %tmp0:_(s16) = G_AND %unknown, %mask0455 %val0:_(s16) = G_OR %tmp0, %mask1456 %mask2:_(s16) = G_CONSTANT i16 4096457 %mask3:_(s16) = G_CONSTANT i16 371458 %tmp1:_(s16) = G_AND %unknown, %mask2459 %val1:_(s16) = G_OR %tmp1, %mask3460 %add:_(s16) = G_ADD %val0, %val1461 %copy_add:_(s16) = COPY %add462)";463 464 setUp(MIRString);465 if (!TM)466 GTEST_SKIP();467 468 Register CopyReg = Copies[Copies.size() - 1];469 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);470 Register SrcReg = FinalCopy->getOperand(1).getReg();471 GISelValueTracking Info(*MF);472 KnownBits Res = Info.getKnownBits(SrcReg);473 // Add KnowBits works out known carry bits first and then calculates result.474 // 001?01?101?000?0475 // + 000?000101110011476 // = 0??????01??10??1477 EXPECT_EQ(0x0091u, Res.One.getZExtValue());478 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());479}480 481TEST_F(AArch64GISelMITest, TestKnownBitsSUB) {482 StringRef MIRString = R"(483 %ptr:_(p0) = G_IMPLICIT_DEF484 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))485 %mask0:_(s16) = G_CONSTANT i16 4642486 %mask1:_(s16) = G_CONSTANT i16 9536487 %tmp0:_(s16) = G_AND %unknown, %mask0488 %val0:_(s16) = G_OR %tmp0, %mask1489 %mask2:_(s16) = G_CONSTANT i16 4096490 %mask3:_(s16) = G_CONSTANT i16 371491 %tmp1:_(s16) = G_AND %unknown, %mask2492 %val1:_(s16) = G_OR %tmp1, %mask3493 %sub:_(s16) = G_SUB %val0, %val1494 %copy_sub:_(s16) = COPY %sub495)";496 497 setUp(MIRString);498 if (!TM)499 GTEST_SKIP();500 501 Register CopyReg = Copies[Copies.size() - 1];502 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);503 Register SrcReg = FinalCopy->getOperand(1).getReg();504 GISelValueTracking Info(*MF);505 KnownBits Res = Info.getKnownBits(SrcReg);506 // Sub KnowBits for LHS - RHS use Add KnownBits for LHS + ~RHS + 1.507 EXPECT_EQ(0x01CDu, Res.One.getZExtValue());508 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());509}510 511TEST_F(AArch64GISelMITest, TestKnownBitsMUL) {512 StringRef MIRString = R"(513 %ptr0:_(p0) = G_IMPLICIT_DEF514 %load0:_(s16) = G_LOAD %ptr0(p0) :: (load (s16))515 %mask0:_(s16) = G_CONSTANT i16 4516 %mask1:_(s16) = G_CONSTANT i16 18517 %tmp:_(s16) = G_AND %load0, %mask0518 %val0:_(s16) = G_OR %tmp, %mask1519 %cst:_(s16) = G_CONSTANT i16 12520 %mul:_(s16) = G_MUL %val0, %cst521 %copy_mul:_(s16) = COPY %mul522)";523 524 setUp(MIRString);525 if (!TM)526 GTEST_SKIP();527 528 Register CopyReg = Copies[Copies.size() - 1];529 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);530 Register SrcReg = FinalCopy->getOperand(1).getReg();531 GISelValueTracking Info(*MF);532 KnownBits Res = Info.getKnownBits(SrcReg);533 // Mul KnowBits are conservatively correct, but not guaranteed to be precise.534 // Precise for trailing bits up to the first unknown bit.535 // 00010?10 * 00001100 =536 // 00010?1000537 // + 00010?10000538 // = 0000000010??1000539 // KB 0000000?????1000540 EXPECT_EQ(0x0008u, Res.One.getZExtValue());541 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());542}543 544TEST_F(AArch64GISelMITest, TestKnownBitsICMP) {545 StringRef MIRString = R"(546 %cst0:_(s32) = G_CONSTANT i32 0547 %cst1:_(s32) = G_CONSTANT i32 1548 %icmp:_(s32) = G_ICMP intpred(ne), %cst0, %cst1549 %copy_icmp:_(s32) = COPY %icmp550)";551 552 setUp(MIRString);553 if (!TM)554 GTEST_SKIP();555 556 Register CopyReg = Copies[Copies.size() - 1];557 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);558 Register SrcReg = FinalCopy->getOperand(1).getReg();559 GISelValueTracking Info(*MF);560 KnownBits Res = Info.getKnownBits(SrcReg);561 // For targets that use 0 or 1 as icmp result in large register set high bits562 // to 0, does not analyze operands/compare predicate.563 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());564 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());565}566 567TEST_F(AArch64GISelMITest, TestKnownBitsFCMP) {568 StringRef MIRString = R"(569 %cst0:_(s32) = G_FCONSTANT float 0.0570 %cst1:_(s32) = G_FCONSTANT float 1.0571 %fcmp:_(s32) = G_FCMP floatpred(one), %cst0, %cst1572 %copy_fcmp:_(s32) = COPY %fcmp573)";574 575 setUp(MIRString);576 if (!TM)577 GTEST_SKIP();578 579 Register CopyReg = Copies[Copies.size() - 1];580 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);581 Register SrcReg = FinalCopy->getOperand(1).getReg();582 GISelValueTracking Info(*MF);583 KnownBits Res = Info.getKnownBits(SrcReg);584 // For targets that use 0 or 1 as fcmp result in large register set high bits585 // to 0, does not analyze operands/compare predicate.586 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());587 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());588}589 590TEST_F(AArch64GISelMITest, TestKnownBitsSelect) {591 StringRef MIRString = R"(592 %ptr:_(p0) = G_IMPLICIT_DEF593 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))594 %mask0:_(s8) = G_CONSTANT i8 24595 %mask1:_(s8) = G_CONSTANT i8 224596 %tmp0:_(s8) = G_AND %unknown, %mask0597 %val0:_(s8) = G_OR %tmp0, %mask1598 %mask2:_(s8) = G_CONSTANT i8 146599 %mask3:_(s8) = G_CONSTANT i8 36600 %tmp1:_(s8) = G_AND %unknown, %mask2601 %val1:_(s8) = G_OR %tmp1, %mask3602 %cond:_(s1) = G_CONSTANT i1 false603 %select:_(s8) = G_SELECT %cond, %val0, %val1604 %copy_select:_(s8) = COPY %select605)";606 607 setUp(MIRString);608 if (!TM)609 GTEST_SKIP();610 611 Register CopyReg = Copies[Copies.size() - 1];612 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);613 Register SrcReg = FinalCopy->getOperand(1).getReg();614 GISelValueTracking Info(*MF);615 KnownBits Res = Info.getKnownBits(SrcReg);616 // Select KnownBits takes common bits of LHS and RHS, does not analyze617 // condition operand.618 // 111??000619 // select ?01?01?0620 // = ??1????0621 EXPECT_EQ(0x20u, Res.One.getZExtValue());622 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());623}624 625TEST_F(AArch64GISelMITest, TestKnownBits) {626 627 StringRef MIR = " %3:_(s32) = G_TRUNC %0\n"628 " %4:_(s32) = G_TRUNC %1\n"629 " %5:_(s32) = G_CONSTANT i32 5\n"630 " %6:_(s32) = G_CONSTANT i32 24\n"631 " %7:_(s32) = G_CONSTANT i32 28\n"632 " %14:_(p0) = G_INTTOPTR %7\n"633 " %16:_(s32) = G_PTRTOINT %14\n"634 " %8:_(s32) = G_SHL %3, %5\n"635 " %9:_(s32) = G_SHL %4, %5\n"636 " %10:_(s32) = G_OR %8, %6\n"637 " %11:_(s32) = G_OR %9, %16\n"638 " %12:_(s32) = G_MUL %10, %11\n"639 " %13:_(s32) = COPY %12\n";640 setUp(MIR);641 if (!TM)642 GTEST_SKIP();643 unsigned CopyReg = Copies[Copies.size() - 1];644 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);645 unsigned SrcReg = FinalCopy->getOperand(1).getReg();646 GISelValueTracking Info(*MF);647 KnownBits Known = Info.getKnownBits(SrcReg);648 EXPECT_FALSE(Known.hasConflict());649 EXPECT_EQ(32u, Known.One.getZExtValue());650 EXPECT_EQ(95u, Known.Zero.getZExtValue());651 APInt Zeroes = Info.getKnownZeroes(SrcReg);652 EXPECT_EQ(Known.Zero, Zeroes);653}654 655TEST_F(AArch64GISelMITest, TestSignBitIsZero) {656 setUp();657 if (!TM)658 GTEST_SKIP();659 660 const LLT S32 = LLT::scalar(32);661 auto SignBit = B.buildConstant(S32, 0x80000000);662 auto Zero = B.buildConstant(S32, 0);663 664 GISelValueTracking KnownBits(*MF);665 666 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));667 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));668}669 670TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) {671 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"672 " %4:_(s8) = COPY %3\n"673 674 " %5:_(s8) = G_CONSTANT i8 -1\n"675 " %6:_(s8) = COPY %5\n"676 677 " %7:_(s8) = G_CONSTANT i8 127\n"678 " %8:_(s8) = COPY %7\n"679 680 " %9:_(s8) = G_CONSTANT i8 32\n"681 " %10:_(s8) = COPY %9\n"682 683 " %11:_(s8) = G_CONSTANT i8 -32\n"684 " %12:_(s8) = COPY %11\n";685 setUp(MIRString);686 if (!TM)687 GTEST_SKIP();688 Register CopyReg1 = Copies[Copies.size() - 5];689 Register CopyRegNeg1 = Copies[Copies.size() - 4];690 Register CopyReg127 = Copies[Copies.size() - 3];691 Register CopyReg32 = Copies[Copies.size() - 2];692 Register CopyRegNeg32 = Copies[Copies.size() - 1];693 694 GISelValueTracking Info(*MF);695 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));696 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));697 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));698 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));699 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));700}701 702TEST_F(AArch64GISelMITest, TestNumSignBitsXOR) {703 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"704 " %cn1:_(s8) = G_CONSTANT i8 -1\n"705 " %c127:_(s8) = G_CONSTANT i8 127\n"706 " %c32:_(s8) = G_CONSTANT i8 32\n"707 " %cn32:_(s8) = G_CONSTANT i8 -32\n"708 709 " %xor1:_(s8) = G_XOR %c1, %cn1\n"710 " %Copy1:_(s8) = COPY %xor1\n"711 712 " %xor2:_(s8) = G_XOR %c1, %c32\n"713 " %Copy2:_(s8) = COPY %xor2\n"714 715 " %xor3:_(s8) = G_XOR %c32, %c127\n"716 " %Copy3:_(s8) = COPY %xor3\n"717 718 " %xor4:_(s8) = G_XOR %cn32, %c127\n"719 " %Copy4:_(s8) = COPY %xor4\n"720 721 " %xor5:_(s8) = G_XOR %c127, %cn32\n"722 " %Copy5:_(s8) = COPY %xor5\n";723 setUp(MIRString);724 if (!TM)725 GTEST_SKIP();726 Register Copy1 = Copies[Copies.size() - 5];727 Register Copy2 = Copies[Copies.size() - 4];728 Register Copy3 = Copies[Copies.size() - 3];729 Register Copy4 = Copies[Copies.size() - 2];730 Register Copy5 = Copies[Copies.size() - 1];731 732 GISelValueTracking Info(*MF);733 EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));734 EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));735 EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));736 EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));737 EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));738}739 740TEST_F(AArch64GISelMITest, TestNumSignBitsOR) {741 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"742 " %cn1:_(s8) = G_CONSTANT i8 -1\n"743 " %c127:_(s8) = G_CONSTANT i8 127\n"744 " %c32:_(s8) = G_CONSTANT i8 32\n"745 " %cn32:_(s8) = G_CONSTANT i8 -32\n"746 747 " %or1:_(s8) = G_OR %c1, %cn1\n"748 " %Copy1:_(s8) = COPY %or1\n"749 750 " %or2:_(s8) = G_OR %c1, %c32\n"751 " %Copy2:_(s8) = COPY %or2\n"752 753 " %or3:_(s8) = G_OR %c32, %c127\n"754 " %Copy3:_(s8) = COPY %or3\n"755 756 " %or4:_(s8) = G_OR %cn32, %c127\n"757 " %Copy4:_(s8) = COPY %or4\n"758 759 " %or5:_(s8) = G_OR %c127, %cn32\n"760 " %Copy5:_(s8) = COPY %or5\n";761 setUp(MIRString);762 if (!TM)763 GTEST_SKIP();764 Register Copy1 = Copies[Copies.size() - 5];765 Register Copy2 = Copies[Copies.size() - 4];766 Register Copy3 = Copies[Copies.size() - 3];767 Register Copy4 = Copies[Copies.size() - 2];768 Register Copy5 = Copies[Copies.size() - 1];769 770 GISelValueTracking Info(*MF);771 EXPECT_EQ(8u, Info.computeNumSignBits(Copy1));772 EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));773 EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));774 EXPECT_EQ(8u, Info.computeNumSignBits(Copy4));775 EXPECT_EQ(8u, Info.computeNumSignBits(Copy5));776}777 778TEST_F(AArch64GISelMITest, TestNumSignBitsAND) {779 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"780 " %cn1:_(s8) = G_CONSTANT i8 -1\n"781 " %c127:_(s8) = G_CONSTANT i8 127\n"782 " %c32:_(s8) = G_CONSTANT i8 32\n"783 " %cn32:_(s8) = G_CONSTANT i8 -32\n"784 785 " %and1:_(s8) = G_AND %c1, %cn1\n"786 " %Copy1:_(s8) = COPY %and1\n"787 788 " %and2:_(s8) = G_AND %c1, %c32\n"789 " %Copy2:_(s8) = COPY %and2\n"790 791 " %and3:_(s8) = G_AND %c32, %c127\n"792 " %Copy3:_(s8) = COPY %and3\n"793 794 " %and4:_(s8) = G_AND %cn32, %c127\n"795 " %Copy4:_(s8) = COPY %and4\n"796 797 " %and5:_(s8) = G_AND %c127, %cn32\n"798 " %Copy5:_(s8) = COPY %and5\n";799 setUp(MIRString);800 if (!TM)801 GTEST_SKIP();802 Register Copy1 = Copies[Copies.size() - 5];803 Register Copy2 = Copies[Copies.size() - 4];804 Register Copy3 = Copies[Copies.size() - 3];805 Register Copy4 = Copies[Copies.size() - 2];806 Register Copy5 = Copies[Copies.size() - 1];807 808 GISelValueTracking Info(*MF);809 EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));810 EXPECT_EQ(8u, Info.computeNumSignBits(Copy2));811 EXPECT_EQ(2u, Info.computeNumSignBits(Copy3));812 EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));813 EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));814}815 816TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {817 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"818 " %4:_(s8) = G_LOAD %3 :: (load (s8))\n"819 " %5:_(s32) = G_SEXT %4\n"820 " %6:_(s32) = COPY %5\n"821 822 " %7:_(s8) = G_CONSTANT i8 -1\n"823 " %8:_(s32) = G_SEXT %7\n"824 " %9:_(s32) = COPY %8\n";825 setUp(MIRString);826 if (!TM)827 GTEST_SKIP();828 Register CopySextLoad = Copies[Copies.size() - 2];829 Register CopySextNeg1 = Copies[Copies.size() - 1];830 831 GISelValueTracking Info(*MF);832 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));833 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));834}835 836TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) {837 StringRef MIRString = R"(838 %ptr:_(p0) = G_IMPLICIT_DEF839 %load4:_(s32) = G_LOAD %ptr :: (load (s32))840 841 %inreg7:_(s32) = G_SEXT_INREG %load4, 7842 %copy_inreg7:_(s32) = COPY %inreg7843 844 %inreg8:_(s32) = G_SEXT_INREG %load4, 8845 %copy_inreg8:_(s32) = COPY %inreg8846 847 %inreg9:_(s32) = G_SEXT_INREG %load4, 9848 %copy_inreg9:_(s32) = COPY %inreg9849 850 %inreg31:_(s32) = G_SEXT_INREG %load4, 31851 %copy_inreg31:_(s32) = COPY %inreg31852 853 %load1:_(s8) = G_LOAD %ptr :: (load (s8))854 %sext_load1:_(s32) = G_SEXT %load1855 856 %inreg6_sext:_(s32) = G_SEXT_INREG %sext_load1, 6857 %copy_inreg6_sext:_(s32) = COPY %inreg6_sext858 859 %inreg7_sext:_(s32) = G_SEXT_INREG %sext_load1, 7860 %copy_inreg7_sext:_(s32) = COPY %inreg7_sext861 862 %inreg8_sext:_(s32) = G_SEXT_INREG %sext_load1, 8863 %copy_inreg8_sext:_(s32) = COPY %inreg8_sext864 865 %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9866 %copy_inreg9_sext:_(s32) = COPY %inreg9_sext867 868 %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31869 %copy_inreg31_sext:_(s32) = COPY %inreg31_sext870)";871 872 setUp(MIRString);873 if (!TM)874 GTEST_SKIP();875 876 Register CopyInReg7 = Copies[Copies.size() - 9];877 Register CopyInReg8 = Copies[Copies.size() - 8];878 Register CopyInReg9 = Copies[Copies.size() - 7];879 Register CopyInReg31 = Copies[Copies.size() - 6];880 881 Register CopyInReg6Sext = Copies[Copies.size() - 5];882 Register CopyInReg7Sext = Copies[Copies.size() - 4];883 Register CopyInReg8Sext = Copies[Copies.size() - 3];884 Register CopyInReg9Sext = Copies[Copies.size() - 2];885 Register CopyInReg31Sext = Copies[Copies.size() - 1];886 887 GISelValueTracking Info(*MF);888 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));889 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));890 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));891 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));892 893 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));894 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));895 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));896 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));897 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));898}899 900TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) {901 StringRef MIRString = R"(902 %ptr:_(p0) = G_IMPLICIT_DEF903 %load4:_(s32) = G_LOAD %ptr :: (load (s32))904 905 %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1906 %copy_assert_sext1:_(s32) = COPY %assert_sext1907 908 %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7909 %copy_assert_sext7:_(s32) = COPY %assert_sext7910 911 %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8912 %copy_assert_sext8:_(s32) = COPY %assert_sext8913 914 %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9915 %copy_assert_sext9:_(s32) = COPY %assert_sext9916 917 %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31918 %copy_assert_sext31:_(s32) = COPY %assert_sext31919 920 %load1:_(s8) = G_LOAD %ptr :: (load (s8))921 %sext_load1:_(s32) = G_SEXT %load1922 923 %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6924 %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext925 926 %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7927 %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext928 929 %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8930 %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext931 932 %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9933 %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext934 935 %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31936 %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext937)";938 939 setUp(MIRString);940 if (!TM)941 GTEST_SKIP();942 943 Register CopyInReg1 = Copies[Copies.size() - 10];944 Register CopyInReg7 = Copies[Copies.size() - 9];945 Register CopyInReg8 = Copies[Copies.size() - 8];946 Register CopyInReg9 = Copies[Copies.size() - 7];947 Register CopyInReg31 = Copies[Copies.size() - 6];948 949 Register CopyInReg6Sext = Copies[Copies.size() - 5];950 Register CopyInReg7Sext = Copies[Copies.size() - 4];951 Register CopyInReg8Sext = Copies[Copies.size() - 3];952 Register CopyInReg9Sext = Copies[Copies.size() - 2];953 Register CopyInReg31Sext = Copies[Copies.size() - 1];954 955 GISelValueTracking Info(*MF);956 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));957 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));958 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));959 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));960 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));961 962 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));963 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));964 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));965 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));966 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));967}968 969TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {970 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"971 " %4:_(s32) = G_LOAD %3 :: (load (s32))\n"972 " %5:_(s8) = G_TRUNC %4\n"973 " %6:_(s8) = COPY %5\n"974 975 " %7:_(s32) = G_CONSTANT i32 -1\n"976 " %8:_(s8) = G_TRUNC %7\n"977 " %9:_(s8) = COPY %8\n"978 979 " %10:_(s32) = G_CONSTANT i32 7\n"980 " %11:_(s8) = G_TRUNC %10\n"981 " %12:_(s8) = COPY %11\n";982 setUp(MIRString);983 if (!TM)984 GTEST_SKIP();985 Register CopyTruncLoad = Copies[Copies.size() - 3];986 Register CopyTruncNeg1 = Copies[Copies.size() - 2];987 Register CopyTrunc7 = Copies[Copies.size() - 1];988 989 GISelValueTracking Info(*MF);990 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));991 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));992 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));993}994 995TEST_F(AArch64GISelMITest, TestNumSignBitsCmp) {996 StringRef MIRString =997 " %v1:_(<4 x s32>) = G_IMPLICIT_DEF\n"998 " %v2:_(<4 x s32>) = G_IMPLICIT_DEF\n"999 " %s1:_(s64) = G_IMPLICIT_DEF\n"1000 " %s2:_(s64) = G_IMPLICIT_DEF\n"1001 " %cmp:_(<4 x s32>) = G_FCMP floatpred(ogt), %v1, %v2\n"1002 " %cpy1:_(<4 x s32>) = COPY %cmp\n"1003 " %cmp2:_(<4 x s32>) = G_ICMP intpred(eq), %v1, %v2\n"1004 " %cpy2:_(<4 x s32>) = COPY %cmp2\n"1005 " %cmp3:_(s32) = G_FCMP floatpred(ogt), %s1, %s2\n"1006 " %cpy3:_(s32) = COPY %cmp3\n"1007 " %cmp4:_(s32) = G_ICMP intpred(eq), %s1, %s2\n"1008 " %cpy4:_(s32) = COPY %cmp4\n";1009 1010 setUp(MIRString);1011 if (!TM)1012 GTEST_SKIP();1013 Register CopyVecFCMP = Copies[Copies.size() - 4];1014 Register CopyVecICMP = Copies[Copies.size() - 3];1015 Register CopyScalarFCMP = Copies[Copies.size() - 2];1016 Register CopyScalarICMP = Copies[Copies.size() - 1];1017 1018 GISelValueTracking Info(*MF);1019 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecFCMP));1020 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecICMP));1021 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarFCMP));1022 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarICMP));1023}1024 1025TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {1026 StringRef MIRString =1027 " %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"1028 " %4:_(s32) = G_IMPLICIT_DEF\n"1029 " %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"1030 " %6:_(s32) = COPY %5\n"1031 1032 " %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"1033 " %8:_(s32) = COPY %7\n"1034 1035 " %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"1036 " %10:_(s32) = COPY %9\n"1037 1038 " %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"1039 " %12:_(s32) = COPY %11\n";1040 1041 setUp(MIRString);1042 if (!TM)1043 GTEST_SKIP();1044 1045 Register CopyLoadUByte = Copies[Copies.size() - 4];1046 Register CopyLoadSByte = Copies[Copies.size() - 3];1047 Register CopyLoadUShort = Copies[Copies.size() - 2];1048 Register CopyLoadSShort = Copies[Copies.size() - 1];1049 1050 GISelValueTracking Info(*MF);1051 1052 EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));1053 EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));1054 EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));1055 EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));1056}1057 1058TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {1059 StringRef MIRString =1060 " %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n"1061 " %6:_(p4) = COPY %5\n"1062 " %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n"1063 " %8:_(p4) = COPY %7\n"1064 " %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"1065 " %10:_(p4) = COPY %9\n"1066 " %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"1067 " %12:_(p4) = COPY %11\n"1068 " %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"1069 " %14:_(p4) = COPY %13\n";1070 1071 setUp(MIRString);1072 if (!TM)1073 GTEST_SKIP();1074 1075 Register CopyDispatchPtr = Copies[Copies.size() - 5];1076 Register CopyQueuePtr = Copies[Copies.size() - 4];1077 Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];1078 Register CopyImplicitArgPtr = Copies[Copies.size() - 2];1079 Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];1080 1081 GISelValueTracking Info(*MF);1082 1083 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr));1084 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr));1085 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr));1086 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr));1087 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));1088}1089 1090TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {1091 1092 StringRef MIRString = R"MIR(1093 %zero:_(s32) = G_CONSTANT i32 01094 %one:_(s32) = G_CONSTANT i32 11095 %two:_(s32) = G_CONSTANT i32 21096 %three:_(s32) = G_CONSTANT i32 31097 %five:_(s32) = G_CONSTANT i32 51098 %copy_zero:_(s32) = COPY %zero1099 %copy_one:_(s32) = COPY %one1100 %copy_two:_(s32) = COPY %two1101 %copy_three:_(s32) = COPY %three1102 1103 %trunc_two:_(s1) = G_TRUNC %two1104 %trunc_three:_(s1) = G_TRUNC %three1105 %trunc_five:_(s1) = G_TRUNC %five1106 1107 %copy_trunc_two:_(s1) = COPY %trunc_two1108 %copy_trunc_three:_(s1) = COPY %trunc_three1109 %copy_trunc_five:_(s1) = COPY %trunc_five1110 1111 %ptr:_(p1) = G_IMPLICIT_DEF1112 %shift_amt:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)1113 1114 %shl_1:_(s32) = G_SHL %one, %shift_amt1115 %copy_shl_1:_(s32) = COPY %shl_11116 1117 %shl_2:_(s32) = G_SHL %two, %shift_amt1118 %copy_shl_2:_(s32) = COPY %shl_21119 1120 %not_sign_mask:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)1121 %sign_mask:_(s32) = G_CONSTANT i32 -21474836481122 1123 %lshr_not_sign_mask:_(s32) = G_LSHR %not_sign_mask, %shift_amt1124 %copy_lshr_not_sign_mask:_(s32) = COPY %lshr_not_sign_mask1125 1126 %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt1127 %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask1128 1129 %or_pow2:_(s32) = G_OR %zero, %two1130 %copy_or_pow2:_(s32) = COPY %or_pow21131 1132)MIR";1133 setUp(MIRString);1134 if (!TM)1135 GTEST_SKIP();1136 1137 GISelValueTracking VT(*MF);1138 1139 Register CopyZero = Copies[Copies.size() - 12];1140 Register CopyOne = Copies[Copies.size() - 11];1141 Register CopyTwo = Copies[Copies.size() - 10];1142 Register CopyThree = Copies[Copies.size() - 9];1143 Register CopyTruncTwo = Copies[Copies.size() - 8];1144 Register CopyTruncThree = Copies[Copies.size() - 7];1145 Register CopyTruncFive = Copies[Copies.size() - 6];1146 1147 Register CopyShl1 = Copies[Copies.size() - 5];1148 Register CopyShl2 = Copies[Copies.size() - 4];1149 1150 Register CopyLShrNotSignMask = Copies[Copies.size() - 3];1151 Register CopyLShrSignMask = Copies[Copies.size() - 2];1152 Register CopyOrPow2 = Copies[Copies.size() - 1];1153 1154 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &VT));1155 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &VT));1156 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &VT));1157 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &VT));1158 1159 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &VT));1160 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &VT));1161 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &VT));1162 1163 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &VT));1164 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &VT));1165 1166 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &VT));1167 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &VT));1168 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &VT));1169}1170 1171static void AddRangeMetadata(LLVMContext &Context, MachineInstr *Load) {1172 IntegerType *Int8Ty = Type::getInt8Ty(Context);1173 1174 // Value must be in [0, 2)1175 Metadata *LowAndHigh[] = {1176 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),1177 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};1178 auto NewMDNode = MDNode::get(Context, LowAndHigh);1179 const MachineMemOperand *OldMMO = *Load->memoperands_begin();1180 MachineMemOperand *NewMMO =1181 Load->getParent()->getParent()->getMachineMemOperand(1182 OldMMO->getPointerInfo(), OldMMO->getFlags(), OldMMO->getMemoryType(),1183 OldMMO->getAlign(), OldMMO->getAAInfo(), NewMDNode);1184 MachineIRBuilder MIB(*Load);1185 MIB.buildLoadInstr(Load->getOpcode(), Load->getOperand(0),1186 Load->getOperand(1), *NewMMO);1187 Load->eraseFromParent();1188}1189 1190TEST_F(AArch64GISelMITest, TestMetadata) {1191 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"1192 " %load:_(s8) = G_LOAD %imp(p0) :: (load (s8))\n"1193 " %ext:_(s32) = G_ZEXT %load(s8)\n"1194 " %cst:_(s32) = G_CONSTANT i32 1\n"1195 " %and:_(s32) = G_AND %ext, %cst\n"1196 " %copy:_(s32) = COPY %and(s32)\n";1197 setUp(MIRString);1198 if (!TM)1199 GTEST_SKIP();1200 1201 Register CopyReg = Copies[Copies.size() - 1];1202 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);1203 Register SrcReg = FinalCopy->getOperand(1).getReg();1204 1205 // We need a load with a metadata range for this to break. Fudge the load in1206 // the string and replace it with something we can work with.1207 MachineInstr *And = MRI->getVRegDef(SrcReg);1208 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());1209 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());1210 AddRangeMetadata(Context, Load);1211 1212 GISelValueTracking Info(*MF);1213 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());1214 1215 // We don't know what the result of the load is, so we don't know any ones.1216 EXPECT_TRUE(Res.One.isZero());1217 1218 // We know that the value is in [0, 2). So, we don't know if the first bit1219 // is 0 or not. However, we do know that every other bit must be 0.1220 APInt Mask(Res.getBitWidth(), 1);1221 Mask.flipAllBits();1222 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());1223}1224 1225TEST_F(AArch64GISelMITest, TestMetadataExt) {1226 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"1227 " %load:_(s32) = G_LOAD %imp(p0) :: (load (s8))\n"1228 " %copy:_(s32) = COPY %load(s32)\n";1229 setUp(MIRString);1230 if (!TM)1231 GTEST_SKIP();1232 1233 Register CopyReg = Copies[Copies.size() - 1];1234 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);1235 Register SrcReg = FinalCopy->getOperand(1).getReg();1236 MachineInstr *Load = MRI->getVRegDef(SrcReg);1237 AddRangeMetadata(Context, Load);1238 1239 GISelValueTracking Info(*MF);1240 KnownBits Res = Info.getKnownBits(SrcReg);1241 EXPECT_TRUE(Res.One.isZero());1242 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfeu);1243}1244 1245TEST_F(AArch64GISelMITest, TestMetadataZExt) {1246 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"1247 " %load:_(s32) = G_ZEXTLOAD %imp(p0) :: (load (s8))\n"1248 " %copy:_(s32) = COPY %load(s32)\n";1249 setUp(MIRString);1250 if (!TM)1251 GTEST_SKIP();1252 1253 Register CopyReg = Copies[Copies.size() - 1];1254 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);1255 Register SrcReg = FinalCopy->getOperand(1).getReg();1256 MachineInstr *Load = MRI->getVRegDef(SrcReg);1257 AddRangeMetadata(Context, Load);1258 1259 GISelValueTracking Info(*MF);1260 KnownBits Res = Info.getKnownBits(SrcReg);1261 EXPECT_TRUE(Res.One.isZero());1262 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfffffffe);1263}1264 1265TEST_F(AArch64GISelMITest, TestMetadataSExt) {1266 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"1267 " %load:_(s32) = G_SEXTLOAD %imp(p0) :: (load (s8))\n"1268 " %copy:_(s32) = COPY %load(s32)\n";1269 setUp(MIRString);1270 if (!TM)1271 GTEST_SKIP();1272 1273 Register CopyReg = Copies[Copies.size() - 1];1274 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);1275 Register SrcReg = FinalCopy->getOperand(1).getReg();1276 MachineInstr *Load = MRI->getVRegDef(SrcReg);1277 AddRangeMetadata(Context, Load);1278 1279 GISelValueTracking Info(*MF);1280 KnownBits Res = Info.getKnownBits(SrcReg);1281 EXPECT_TRUE(Res.One.isZero());1282 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfffffffe);1283}1284 1285TEST_F(AArch64GISelMITest, TestKnownBitsExt) {1286 StringRef MIRString = " %c1:_(s16) = G_CONSTANT i16 1\n"1287 " %x:_(s16) = G_IMPLICIT_DEF\n"1288 " %y:_(s16) = G_AND %x, %c1\n"1289 " %anyext:_(s32) = G_ANYEXT %y(s16)\n"1290 " %r1:_(s32) = COPY %anyext\n"1291 " %zext:_(s32) = G_ZEXT %y(s16)\n"1292 " %r2:_(s32) = COPY %zext\n"1293 " %sext:_(s32) = G_SEXT %y(s16)\n"1294 " %r3:_(s32) = COPY %sext\n";1295 setUp(MIRString);1296 if (!TM)1297 GTEST_SKIP();1298 Register CopyRegAny = Copies[Copies.size() - 3];1299 Register CopyRegZ = Copies[Copies.size() - 2];1300 Register CopyRegS = Copies[Copies.size() - 1];1301 1302 GISelValueTracking Info(*MF);1303 MachineInstr *Copy;1304 Register SrcReg;1305 KnownBits Res;1306 1307 Copy = MRI->getVRegDef(CopyRegAny);1308 SrcReg = Copy->getOperand(1).getReg();1309 Res = Info.getKnownBits(SrcReg);1310 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1311 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1312 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());1313 1314 Copy = MRI->getVRegDef(CopyRegZ);1315 SrcReg = Copy->getOperand(1).getReg();1316 Res = Info.getKnownBits(SrcReg);1317 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1318 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1319 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());1320 1321 Copy = MRI->getVRegDef(CopyRegS);1322 SrcReg = Copy->getOperand(1).getReg();1323 Res = Info.getKnownBits(SrcReg);1324 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1325 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1326 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());1327}1328 1329TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {1330 StringRef MIRString = R"(1331 ; 000...00011332 %one:_(s32) = G_CONSTANT i32 11333 1334 ; 000...00101335 %two:_(s32) = G_CONSTANT i32 21336 1337 ; 000...10101338 %ten:_(s32) = G_CONSTANT i32 101339 1340 ; ???...????1341 %w0:_(s32) = COPY $w01342 1343 ; ???...?1?1344 %or:_(s32) = G_OR %w0, %two1345 1346 ; All bits are known.1347 %inreg1:_(s32) = G_SEXT_INREG %one, 11348 %copy_inreg1:_(s32) = COPY %inreg11349 1350 ; All bits unknown1351 %inreg2:_(s32) = G_SEXT_INREG %or, 11352 %copy_inreg2:_(s32) = COPY %inreg21353 1354 ; Extending from the only (known) set bit1355 ; 111...11?1356 %inreg3:_(s32) = G_SEXT_INREG %or, 21357 %copy_inreg3:_(s32) = COPY %inreg31358 1359 ; Extending from a known set bit, overwriting all of the high set bits.1360 ; 111...11101361 %inreg4:_(s32) = G_SEXT_INREG %ten, 21362 %copy_inreg4:_(s32) = COPY %inreg41363 1364)";1365 setUp(MIRString);1366 if (!TM)1367 GTEST_SKIP();1368 GISelValueTracking Info(*MF);1369 KnownBits Res;1370 auto GetKB = [&](unsigned Idx) {1371 Register CopyReg = Copies[Idx];1372 auto *Copy = MRI->getVRegDef(CopyReg);1373 return Info.getKnownBits(Copy->getOperand(1).getReg());1374 };1375 1376 // Every bit is known to be a 1.1377 Res = GetKB(Copies.size() - 4);1378 EXPECT_EQ(32u, Res.getBitWidth());1379 EXPECT_TRUE(Res.isAllOnes());1380 1381 // All bits are unknown1382 Res = GetKB(Copies.size() - 3);1383 EXPECT_EQ(32u, Res.getBitWidth());1384 EXPECT_TRUE(Res.isUnknown());1385 1386 // Extending from the only known set bit1387 // 111...11?1388 Res = GetKB(Copies.size() - 2);1389 EXPECT_EQ(32u, Res.getBitWidth());1390 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1391 EXPECT_EQ(0u, Res.Zero.getZExtValue());1392 1393 // Extending from a known set bit, overwriting all of the high set bits.1394 // 111...11101395 Res = GetKB(Copies.size() - 1);1396 EXPECT_EQ(32u, Res.getBitWidth());1397 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1398 EXPECT_EQ(1u, Res.Zero.getZExtValue());1399}1400 1401TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {1402 StringRef MIRString = R"(1403 ; 000...00011404 %one:_(s32) = G_CONSTANT i32 11405 1406 ; 000...00101407 %two:_(s32) = G_CONSTANT i32 21408 1409 ; 000...10101410 %ten:_(s32) = G_CONSTANT i32 101411 1412 ; ???...????1413 %w0:_(s32) = COPY $w01414 1415 ; ???...?1?1416 %or:_(s32) = G_OR %w0, %two1417 1418 ; All bits are known.1419 %assert_sext1:_(s32) = G_ASSERT_SEXT %one, 11420 %copy_assert_sext1:_(s32) = COPY %assert_sext11421 1422 ; All bits unknown1423 %assert_sext2:_(s32) = G_ASSERT_SEXT %or, 11424 %copy_assert_sext2:_(s32) = COPY %assert_sext21425 1426 ; Extending from the only (known) set bit1427 ; 111...11?1428 %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 21429 %copy_assert_sext3:_(s32) = COPY %assert_sext31430 1431 ; Extending from a known set bit, overwriting all of the high set bits.1432 ; 111...11101433 %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 21434 %copy_assert_sext4:_(s32) = COPY %assert_sext41435)";1436 setUp(MIRString);1437 if (!TM)1438 GTEST_SKIP();1439 GISelValueTracking Info(*MF);1440 KnownBits Res;1441 auto GetKB = [&](unsigned Idx) {1442 Register CopyReg = Copies[Idx];1443 auto *Copy = MRI->getVRegDef(CopyReg);1444 return Info.getKnownBits(Copy->getOperand(1).getReg());1445 };1446 1447 // Every bit is known to be a 1.1448 Res = GetKB(Copies.size() - 4);1449 EXPECT_EQ(32u, Res.getBitWidth());1450 EXPECT_TRUE(Res.isAllOnes());1451 1452 // All bits are unknown1453 Res = GetKB(Copies.size() - 3);1454 EXPECT_EQ(32u, Res.getBitWidth());1455 EXPECT_TRUE(Res.isUnknown());1456 1457 // Extending from the only known set bit1458 // 111...11?1459 Res = GetKB(Copies.size() - 2);1460 EXPECT_EQ(32u, Res.getBitWidth());1461 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1462 EXPECT_EQ(0u, Res.Zero.getZExtValue());1463 1464 // Extending from a known set bit, overwriting all of the high set bits.1465 // 111...11101466 Res = GetKB(Copies.size() - 1);1467 EXPECT_EQ(32u, Res.getBitWidth());1468 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1469 EXPECT_EQ(1u, Res.Zero.getZExtValue());1470}1471 1472TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {1473 StringRef MIRString = R"(1474 %val0:_(s16) = G_CONSTANT i16 352241475 %val1:_(s16) = G_CONSTANT i16 174941476 %val2:_(s16) = G_CONSTANT i16 46591477 %val3:_(s16) = G_CONSTANT i16 439811478 %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val31479 %mergecopy:_(s64) = COPY %merge1480)";1481 setUp(MIRString);1482 if (!TM)1483 GTEST_SKIP();1484 1485 const uint64_t TestVal = UINT64_C(0xabcd123344568998);1486 Register CopyMerge = Copies[Copies.size() - 1];1487 1488 GISelValueTracking Info(*MF);1489 KnownBits Res = Info.getKnownBits(CopyMerge);1490 EXPECT_EQ(64u, Res.getBitWidth());1491 EXPECT_EQ(TestVal, Res.One.getZExtValue());1492 EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());1493}1494 1495TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) {1496 StringRef MIRString = R"(1497 %val:_(s64) = G_CONSTANT i64 123795709621105156081498 %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val1499 %part0:_(s16) = COPY %val01500 %part1:_(s16) = COPY %val11501 %part2:_(s16) = COPY %val21502 %part3:_(s16) = COPY %val31503 1504)";1505 setUp(MIRString);1506 if (!TM)1507 GTEST_SKIP();1508 1509 const uint64_t TestVal = UINT64_C(0xabcd123344568998);1510 GISelValueTracking Info(*MF);1511 1512 int Offset = -4;1513 for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) {1514 Register Part = Copies[Copies.size() + Offset];1515 KnownBits PartKnown = Info.getKnownBits(Part);1516 EXPECT_EQ(16u, PartKnown.getBitWidth());1517 1518 uint16_t PartTestVal = static_cast<uint16_t>(TestVal >> BitOffset);1519 EXPECT_EQ(PartTestVal, PartKnown.One.getZExtValue());1520 EXPECT_EQ(static_cast<uint16_t>(~PartTestVal), PartKnown.Zero.getZExtValue());1521 }1522}1523 1524TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {1525 StringRef MIRString = R"(1526 %const:_(s32) = G_CONSTANT i32 2874540201527 %bswap:_(s32) = G_BSWAP %const1528 %bitreverse:_(s32) = G_BITREVERSE %const1529 %copy_bswap:_(s32) = COPY %bswap1530 %copy_bitreverse:_(s32) = COPY %bitreverse1531)";1532 setUp(MIRString);1533 if (!TM)1534 GTEST_SKIP();1535 1536 const uint32_t ByteSwappedVal = 0x44332211;1537 const uint32_t BitSwappedVal = 0x22cc4488;1538 1539 Register CopyBSwap = Copies[Copies.size() - 2];1540 Register CopyBitReverse = Copies[Copies.size() - 1];1541 1542 GISelValueTracking Info(*MF);1543 1544 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);1545 EXPECT_EQ(32u, BSwapKnown.getBitWidth());1546 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());1547 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());1548 1549 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);1550 EXPECT_EQ(32u, BitReverseKnown.getBitWidth());1551 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());1552 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());1553}1554 1555TEST_F(AArch64GISelMITest, TestKnownBitsUMAX) {1556 StringRef MIRString = R"(1557 %ptr:_(p0) = G_IMPLICIT_DEF1558 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))1559 %mask0:_(s8) = G_CONSTANT i8 101560 %mask1:_(s8) = G_CONSTANT i8 11561 %tmp0:_(s8) = G_AND %unknown, %mask01562 %val0:_(s8) = G_OR %tmp0, %mask11563 %mask2:_(s8) = G_CONSTANT i8 31564 %mask3:_(s8) = G_CONSTANT i8 121565 %tmp1:_(s8) = G_AND %unknown, %mask21566 %val1:_(s8) = G_OR %tmp1, %mask31567 %umax0:_(s8) = G_UMAX %val0, %val11568 %copy_umax0:_(s8) = COPY %umax01569 1570 %mask4:_(s8) = G_CONSTANT i8 141571 %mask5:_(s8) = G_CONSTANT i8 21572 %tmp3:_(s8) = G_AND %unknown, %mask41573 %val3:_(s8) = G_OR %tmp3, %mask51574 %mask6:_(s8) = G_CONSTANT i8 41575 %mask7:_(s8) = G_CONSTANT i8 111576 %tmp4:_(s8) = G_AND %unknown, %mask61577 %val4:_(s8) = G_OR %tmp4, %mask71578 %umax1:_(s8) = G_UMAX %val3, %val41579 %copy_umax1:_(s8) = COPY %umax11580)";1581 1582 setUp(MIRString);1583 if (!TM)1584 GTEST_SKIP();1585 1586 Register CopyReg0 = Copies[Copies.size() - 2];1587 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1588 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1589 GISelValueTracking Info(*MF);1590 // Compares min/max of LHS and RHS, min uses 0 for unknown bits, max uses 1.1591 // If min(LHS) >= max(RHS) returns KnownBits for LHS, similar for RHS. If this1592 // fails tries to calculate individual bits: common bits for both operands and1593 // a few leading bits in some cases.1594 // 0000?0?11595 // umax 000011??1596 // = 000011??1597 KnownBits Res0 = Info.getKnownBits(SrcReg0);1598 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());1599 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());1600 1601 Register CopyReg1 = Copies[Copies.size() - 1];1602 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);1603 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();1604 KnownBits Res1 = Info.getKnownBits(SrcReg1);1605 // 0000??101606 // umax 00001?111607 // = 00001?1?1608 EXPECT_EQ(0x0Au, Res1.One.getZExtValue());1609 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());1610}1611 1612TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {1613 StringRef MIRString = R"(1614 %val:_(s32) = COPY $w01615 %zext:_(s64) = G_ZEXT %val1616 %const:_(s64) = G_CONSTANT i64 -2561617 %umax:_(s64) = G_UMAX %zext, %const1618 %copy_umax:_(s64) = COPY %umax1619)";1620 setUp(MIRString);1621 if (!TM)1622 GTEST_SKIP();1623 1624 Register CopyUMax = Copies[Copies.size() - 1];1625 GISelValueTracking Info(*MF);1626 1627 KnownBits KnownUmax = Info.getKnownBits(CopyUMax);1628 EXPECT_EQ(64u, KnownUmax.getBitWidth());1629 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());1630 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());1631 1632 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());1633 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());1634}1635 1636TEST_F(AArch64GISelMITest, TestKnownBitsUMIN) {1637 StringRef MIRString = R"(1638 %ptr:_(p0) = G_IMPLICIT_DEF1639 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))1640 %mask0:_(s8) = G_CONSTANT i8 101641 %mask1:_(s8) = G_CONSTANT i8 11642 %tmp0:_(s8) = G_AND %unknown, %mask01643 %val0:_(s8) = G_OR %tmp0, %mask11644 %mask2:_(s8) = G_CONSTANT i8 31645 %mask3:_(s8) = G_CONSTANT i8 121646 %tmp1:_(s8) = G_AND %unknown, %mask21647 %val1:_(s8) = G_OR %tmp1, %mask31648 %umin:_(s8) = G_UMIN %val0, %val11649 %copy_umin:_(s8) = COPY %umin1650)";1651 1652 setUp(MIRString);1653 if (!TM)1654 GTEST_SKIP();1655 1656 Register CopyReg0 = Copies[Copies.size() - 1];1657 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1658 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1659 GISelValueTracking Info(*MF);1660 KnownBits Res0 = Info.getKnownBits(SrcReg0);1661 // Flips the range of operands: [0, 0xFFFFFFFF] <-> [0xFFFFFFFF, 0],1662 // uses umax and flips result back.1663 // 0000?0?11664 // umin 000011??1665 // = 0000?0?11666 EXPECT_EQ(0x01u, Res0.One.getZExtValue());1667 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());1668}1669 1670TEST_F(AArch64GISelMITest, TestKnownBitsSMAX) {1671 StringRef MIRString = R"(1672 %ptr:_(p0) = G_IMPLICIT_DEF1673 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))1674 %mask0:_(s8) = G_CONSTANT i8 1281675 %mask1:_(s8) = G_CONSTANT i8 641676 %tmp0:_(s8) = G_AND %unknown, %mask01677 %val0:_(s8) = G_OR %tmp0, %mask11678 %mask2:_(s8) = G_CONSTANT i8 11679 %mask3:_(s8) = G_CONSTANT i8 1281680 %tmp1:_(s8) = G_AND %unknown, %mask21681 %val1:_(s8) = G_OR %tmp1, %mask31682 %smax:_(s8) = G_SMAX %val0, %val11683 %copy_smax:_(s8) = COPY %smax1684)";1685 1686 setUp(MIRString);1687 if (!TM)1688 GTEST_SKIP();1689 1690 Register CopyReg0 = Copies[Copies.size() - 1];1691 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1692 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1693 GISelValueTracking Info(*MF);1694 KnownBits Res0 = Info.getKnownBits(SrcReg0);1695 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0, 0xFFFFFFFF],1696 // uses umax and flips result back.1697 // RHS is negative, LHS is either positive or negative with smaller abs value.1698 // ?10000001699 // smax 1000000?1700 // = ?10000001701 EXPECT_EQ(0x40u, Res0.One.getZExtValue());1702 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());1703}1704 1705TEST_F(AArch64GISelMITest, TestKnownBitsSMIN) {1706 StringRef MIRString = R"(1707 %ptr:_(p0) = G_IMPLICIT_DEF1708 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))1709 %mask0:_(s8) = G_CONSTANT i8 1281710 %mask1:_(s8) = G_CONSTANT i8 641711 %tmp0:_(s8) = G_AND %unknown, %mask01712 %val0:_(s8) = G_OR %tmp0, %mask11713 %mask2:_(s8) = G_CONSTANT i8 11714 %mask3:_(s8) = G_CONSTANT i8 1281715 %tmp1:_(s8) = G_AND %unknown, %mask21716 %val1:_(s8) = G_OR %tmp1, %mask31717 %smin:_(s8) = G_SMIN %val0, %val11718 %copy_smin:_(s8) = COPY %smin1719)";1720 1721 setUp(MIRString);1722 if (!TM)1723 GTEST_SKIP();1724 1725 Register CopyReg0 = Copies[Copies.size() - 1];1726 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1727 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1728 GISelValueTracking Info(*MF);1729 KnownBits Res0 = Info.getKnownBits(SrcReg0);1730 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0xFFFFFFFF, 0],1731 // uses umax and flips result back.1732 // RHS is negative, LHS is either positive or negative with smaller abs value.1733 // ?10000001734 // smin 1000000?1735 // = 1000000?1736 EXPECT_EQ(0x80u, Res0.One.getZExtValue());1737 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());1738}1739 1740TEST_F(AArch64GISelMITest, TestInvalidQueries) {1741 StringRef MIRString = R"(1742 %src:_(s32) = COPY $w01743 %thirty2:_(s32) = G_CONSTANT i32 321744 %equalSized:_(s32) = G_SHL %src, %thirty21745 %copy1:_(s32) = COPY %equalSized1746 %thirty3:_(s32) = G_CONSTANT i32 331747 %biggerSized:_(s32) = G_SHL %src, %thirty31748 %copy2:_(s32) = COPY %biggerSized1749)";1750 setUp(MIRString);1751 if (!TM)1752 GTEST_SKIP();1753 1754 Register EqSizedCopyReg = Copies[Copies.size() - 2];1755 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);1756 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();1757 1758 Register BiggerSizedCopyReg = Copies[Copies.size() - 1];1759 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);1760 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();1761 1762 GISelValueTracking Info(*MF);1763 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);1764 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);1765 1766 1767 // Result can be anything, but we should not crash.1768 EXPECT_TRUE(EqSizeRes.One.isZero());1769 EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());1770 1771 EXPECT_TRUE(BiggerSizeRes.One.isZero());1772 EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());1773}1774 1775TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {1776 StringRef MIRString = R"(1777 %copy:_(s64) = COPY $x01778 1779 %assert8:_(s64) = G_ASSERT_ZEXT %copy, 81780 %copy_assert8:_(s64) = COPY %assert81781 1782 %assert1:_(s64) = G_ASSERT_ZEXT %copy, 11783 %copy_assert1:_(s64) = COPY %assert11784 1785 %assert63:_(s64) = G_ASSERT_ZEXT %copy, 631786 %copy_assert63:_(s64) = COPY %assert631787 1788 %assert3:_(s64) = G_ASSERT_ZEXT %copy, 31789 %copy_assert3:_(s64) = COPY %assert31790)";1791 1792 setUp(MIRString);1793 if (!TM)1794 GTEST_SKIP();1795 1796 Register CopyAssert8 = Copies[Copies.size() - 4];1797 Register CopyAssert1 = Copies[Copies.size() - 3];1798 Register CopyAssert63 = Copies[Copies.size() - 2];1799 Register CopyAssert3 = Copies[Copies.size() - 1];1800 1801 GISelValueTracking Info(*MF);1802 MachineInstr *Copy;1803 Register SrcReg;1804 KnownBits Res;1805 1806 // Assert zero-extension from an 8-bit value.1807 Copy = MRI->getVRegDef(CopyAssert8);1808 SrcReg = Copy->getOperand(1).getReg();1809 Res = Info.getKnownBits(SrcReg);1810 EXPECT_EQ(64u, Res.getBitWidth());1811 EXPECT_EQ(0u, Res.One.getZExtValue());1812 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());1813 1814 // Assert zero-extension from a 1-bit value.1815 Copy = MRI->getVRegDef(CopyAssert1);1816 SrcReg = Copy->getOperand(1).getReg();1817 Res = Info.getKnownBits(SrcReg);1818 EXPECT_EQ(64u, Res.getBitWidth());1819 EXPECT_EQ(0u, Res.One.getZExtValue());1820 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());1821 1822 // Assert zero-extension from a 63-bit value.1823 Copy = MRI->getVRegDef(CopyAssert63);1824 SrcReg = Copy->getOperand(1).getReg();1825 Res = Info.getKnownBits(SrcReg);1826 EXPECT_EQ(64u, Res.getBitWidth());1827 EXPECT_EQ(0u, Res.One.getZExtValue());1828 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());1829 1830 // Assert zero-extension from a 3-bit value.1831 Copy = MRI->getVRegDef(CopyAssert3);1832 SrcReg = Copy->getOperand(1).getReg();1833 Res = Info.getKnownBits(SrcReg);1834 EXPECT_EQ(64u, Res.getBitWidth());1835 EXPECT_EQ(0u, Res.One.getZExtValue());1836 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());1837}1838 1839TEST_F(AArch64GISelMITest, TestKnownBitsCTPOP) {1840 StringRef MIRString = R"(1841 %src:_(s32) = COPY $w01842 %unknown:_(s32) = G_CTPOP %src1843 %unknown_copy:_(s32) = COPY %unknown1844 %constant_4294967295:_(s32) = G_CONSTANT i32 42949672951845 %thirtytwo:_(s32) = G_CTPOP %constant_42949672951846 %thirtytwo_copy:_(s32) = COPY %thirtytwo1847 %constant_15:_(s32) = G_CONSTANT i32 151848 %four:_(s32) = G_CTPOP %constant_151849 %four_copy:_(s32) = COPY %four1850 %constant_1:_(s32) = G_CONSTANT i32 11851 %one:_(s32) = G_CTPOP %constant_11852 %one_copy:_(s32) = COPY %one1853)";1854 setUp(MIRString);1855 if (!TM)1856 GTEST_SKIP();1857 1858 Register UnknownCopy = Copies[Copies.size() - 4];1859 Register ThirtytwoCopy = Copies[Copies.size() - 3];1860 Register FourCopy = Copies[Copies.size() - 2];1861 Register OneCopy = Copies[Copies.size() - 1];1862 1863 GISelValueTracking Info(*MF);1864 MachineInstr *Copy;1865 Register SrcReg;1866 KnownBits Res;1867 1868 Copy = MRI->getVRegDef(UnknownCopy);1869 SrcReg = Copy->getOperand(1).getReg();1870 Res = Info.getKnownBits(SrcReg);1871 EXPECT_EQ(32u, Res.getBitWidth());1872 EXPECT_EQ(0u, Res.One.getZExtValue());1873 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());1874 1875 Copy = MRI->getVRegDef(ThirtytwoCopy);1876 SrcReg = Copy->getOperand(1).getReg();1877 Res = Info.getKnownBits(SrcReg);1878 EXPECT_EQ(32u, Res.getBitWidth());1879 EXPECT_EQ(0u, Res.One.getZExtValue());1880 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());1881 1882 Copy = MRI->getVRegDef(FourCopy);1883 SrcReg = Copy->getOperand(1).getReg();1884 Res = Info.getKnownBits(SrcReg);1885 EXPECT_EQ(32u, Res.getBitWidth());1886 EXPECT_EQ(0u, Res.One.getZExtValue());1887 EXPECT_EQ(0xFFFFFFF8u, Res.Zero.getZExtValue());1888 1889 Copy = MRI->getVRegDef(OneCopy);1890 SrcReg = Copy->getOperand(1).getReg();1891 Res = Info.getKnownBits(SrcReg);1892 EXPECT_EQ(32u, Res.getBitWidth());1893 EXPECT_EQ(0u, Res.One.getZExtValue());1894 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());1895}1896 1897TEST_F(AMDGPUGISelMITest, TestKnownBitsUBFX) {1898 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"1899 " %4:_(s32) = G_CONSTANT i32 12\n"1900 " %5:_(s32) = G_CONSTANT i32 8\n"1901 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"1902 " %ubfx_copy:_(s32) = COPY %6\n"1903 " %7:_(s32) = G_CONSTANT i32 28672\n"1904 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"1905 " %ubfx_copy_val:_(s32) = COPY %8\n"1906 " %9:_(s32) = G_IMPLICIT_DEF\n"1907 " %10:_(s32) = G_IMPLICIT_DEF\n"1908 " %11:_(s32) = G_UBFX %3, %9(s32), %10\n"1909 " %ubfx_copy_unk:_(s32) = COPY %11\n"1910 " %12:_(s32) = G_UBFX %3, %9(s32), %5\n"1911 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"1912 " %13:_(s32) = G_UBFX %3, %4(s32), %10\n"1913 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";1914 setUp(MIRString);1915 if (!TM)1916 GTEST_SKIP();1917 Register CopyBfxReg = Copies[Copies.size() - 5];1918 Register CopyValBfxReg = Copies[Copies.size() - 4];1919 Register CopyUnkBfxReg = Copies[Copies.size() - 3];1920 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];1921 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];1922 1923 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);1924 Register SrcReg = CopyBfx->getOperand(1).getReg();1925 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);1926 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();1927 MachineInstr *CopyUnkBfx = MRI->getVRegDef(CopyUnkBfxReg);1928 Register UnkSrcReg = CopyUnkBfx->getOperand(1).getReg();1929 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);1930 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();1931 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);1932 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();1933 1934 GISelValueTracking Info(*MF);1935 1936 KnownBits Res1 = Info.getKnownBits(SrcReg);1937 EXPECT_EQ(0u, Res1.One.getZExtValue());1938 EXPECT_EQ(0xffffff00u, Res1.Zero.getZExtValue());1939 1940 KnownBits Res2 = Info.getKnownBits(ValSrcReg);1941 EXPECT_EQ(7u, Res2.One.getZExtValue());1942 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());1943 1944 KnownBits Res3 = Info.getKnownBits(UnkSrcReg);1945 EXPECT_EQ(0u, Res3.One.getZExtValue());1946 EXPECT_EQ(0u, Res3.Zero.getZExtValue());1947 1948 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);1949 EXPECT_EQ(0u, Res4.One.getZExtValue());1950 EXPECT_EQ(0xffffff00u, Res4.Zero.getZExtValue());1951 1952 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);1953 EXPECT_EQ(0u, Res5.One.getZExtValue());1954 EXPECT_EQ(0xfff00000u, Res5.Zero.getZExtValue());1955}1956 1957TEST_F(AMDGPUGISelMITest, TestKnownBitsSBFX) {1958 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"1959 " %4:_(s32) = G_CONSTANT i32 8\n"1960 " %5:_(s32) = G_CONSTANT i32 4\n"1961 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"1962 " %sbfx_copy:_(s32) = COPY %6\n"1963 " %7:_(s32) = G_CONSTANT i32 2047\n"1964 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"1965 " %sbfx_copy_val:_(s32) = COPY %8\n"1966 " %9:_(s32) = G_CONSTANT i32 2048\n"1967 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"1968 " %sbfx_copy_neg_val:_(s32) = COPY %10\n"1969 " %11:_(s32) = G_IMPLICIT_DEF\n"1970 " %12:_(s32) = G_SBFX %7, %11(s32), %5\n"1971 " %sbfx_copy_unk_off:_(s32) = COPY %12\n"1972 " %13:_(s32) = G_SBFX %9, %4(s32), %11\n"1973 " %sbfx_copy_unk_width:_(s32) = COPY %13\n";1974 setUp(MIRString);1975 if (!TM)1976 GTEST_SKIP();1977 Register CopyBfxReg = Copies[Copies.size() - 5];1978 Register CopyValBfxReg = Copies[Copies.size() - 4];1979 Register CopyNegValBfxReg = Copies[Copies.size() - 3];1980 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];1981 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];1982 1983 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);1984 Register SrcReg = CopyBfx->getOperand(1).getReg();1985 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);1986 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();1987 MachineInstr *CopyNegValBfx = MRI->getVRegDef(CopyNegValBfxReg);1988 Register NegValSrcReg = CopyNegValBfx->getOperand(1).getReg();1989 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);1990 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();1991 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);1992 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();1993 1994 GISelValueTracking Info(*MF);1995 1996 KnownBits Res1 = Info.getKnownBits(SrcReg);1997 EXPECT_EQ(0u, Res1.One.getZExtValue());1998 EXPECT_EQ(0u, Res1.Zero.getZExtValue());1999 2000 KnownBits Res2 = Info.getKnownBits(ValSrcReg);2001 EXPECT_EQ(7u, Res2.One.getZExtValue());2002 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());2003 2004 KnownBits Res3 = Info.getKnownBits(NegValSrcReg);2005 EXPECT_EQ(0xfffffff8u, Res3.One.getZExtValue());2006 EXPECT_EQ(7u, Res3.Zero.getZExtValue());2007 2008 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);2009 EXPECT_EQ(0u, Res4.One.getZExtValue());2010 EXPECT_EQ(0u, Res4.Zero.getZExtValue());2011 2012 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);2013 EXPECT_EQ(0u, Res5.One.getZExtValue());2014 EXPECT_EQ(0u, Res5.Zero.getZExtValue());2015}2016 2017TEST_F(AMDGPUGISelMITest, TestNumSignBitsUBFX) {2018 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"2019 " %4:_(s32) = G_CONSTANT i32 12\n"2020 " %5:_(s32) = G_CONSTANT i32 8\n"2021 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"2022 " %ubfx_copy_unk:_(s32) = COPY %6\n"2023 " %7:_(s32) = G_CONSTANT i32 28672\n"2024 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"2025 " %ubfx_copy_pos:_(s32) = COPY %8\n"2026 " %9:_(s32) = G_CONSTANT i32 -1\n"2027 " %10:_(s32) = G_UBFX %9, %4(s32), %5\n"2028 " %ubfx_copy_neg:_(s32) = COPY %10\n"2029 " %11:_(s32) = G_IMPLICIT_DEF\n"2030 " %12:_(s32) = G_UBFX %7, %11(s32), %5\n"2031 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"2032 " %13:_(s32) = G_UBFX %7, %4(s32), %11\n"2033 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";2034 setUp(MIRString);2035 if (!TM)2036 GTEST_SKIP();2037 Register CopyUnkBfxReg = Copies[Copies.size() - 5];2038 Register CopyPosBfxReg = Copies[Copies.size() - 4];2039 Register CopyNegBfxReg = Copies[Copies.size() - 3];2040 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];2041 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];2042 2043 GISelValueTracking Info(*MF);2044 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkBfxReg));2045 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));2046 EXPECT_EQ(24u, Info.computeNumSignBits(CopyNegBfxReg));2047 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkOffBfxReg));2048 EXPECT_EQ(29u, Info.computeNumSignBits(CopyUnkWidthBfxReg));2049}2050 2051TEST_F(AMDGPUGISelMITest, TestNumSignBitsSBFX) {2052 StringRef MIRString = " %3:_(s32) = G_CONSTANT i32 -1\n"2053 " %4:_(s32) = G_CONSTANT i32 8\n"2054 " %5:_(s32) = G_CONSTANT i32 4\n"2055 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"2056 " %sbfx_copy_neg:_(s32) = COPY %6\n"2057 " %7:_(s32) = G_CONSTANT i32 2047\n"2058 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"2059 " %sbfx_copy_pos:_(s32) = COPY %8\n"2060 " %9:_(s32) = G_CONSTANT i32 2048\n"2061 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"2062 " %sbfx_copy_hiset:_(s32) = COPY %10\n"2063 " %11:_(s32) = G_IMPLICIT_DEF\n"2064 " %12:_(s32) = G_SBFX %11, %4(s32), %5\n"2065 " %sbfx_copy_unk:_(s32) = COPY %12\n"2066 " %13:_(s32) = G_SBFX %3, %11(s32), %5\n"2067 " %sbfx_copy_unk_off:_(s32) = COPY %13\n";2068 setUp(MIRString);2069 if (!TM)2070 GTEST_SKIP();2071 Register CopyNegBfxReg = Copies[Copies.size() - 5];2072 Register CopyPosBfxReg = Copies[Copies.size() - 4];2073 Register CopyHiSetBfxReg = Copies[Copies.size() - 3];2074 Register CopyUnkValBfxReg = Copies[Copies.size() - 2];2075 Register CopyUnkOffBfxReg = Copies[Copies.size() - 1];2076 2077 GISelValueTracking Info(*MF);2078 EXPECT_EQ(32u, Info.computeNumSignBits(CopyNegBfxReg));2079 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));2080 EXPECT_EQ(29u, Info.computeNumSignBits(CopyHiSetBfxReg));2081 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkValBfxReg));2082 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkOffBfxReg));2083}2084 2085TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {2086 StringRef MIRString = R"MIR(2087 %val:_(s64) = COPY $vgpr0_vgpr12088 %ptrval:_(p1) = COPY $vgpr0_vgpr12089 2090 %assert_align1:_(s64) = G_ASSERT_ALIGN %val, 12091 %copy_assert_align1:_(s64) = COPY %assert_align12092 2093 %assert_align2:_(s64) = G_ASSERT_ALIGN %val, 22094 %copy_assert_align2:_(s64) = COPY %assert_align22095 2096 %assert_align4:_(s64) = G_ASSERT_ALIGN %val, 42097 %copy_assert_align4:_(s64) = COPY %assert_align42098 2099 %assert_align8:_(s64) = G_ASSERT_ALIGN %val, 82100 %copy_assert_align8:_(s64) = COPY %assert_align82101 2102 %assert_align16:_(s64) = G_ASSERT_ALIGN %val, 162103 %copy_assert_maxalign:_(s64) = COPY %assert_align162104)MIR";2105 setUp(MIRString);2106 if (!TM)2107 GTEST_SKIP();2108 GISelValueTracking Info(*MF);2109 2110 KnownBits Res;2111 auto GetKB = [&](unsigned Idx) {2112 Register CopyReg = Copies[Idx];2113 auto *Copy = MRI->getVRegDef(CopyReg);2114 return Info.getKnownBits(Copy->getOperand(1).getReg());2115 };2116 2117 auto CheckBits = [&](unsigned NumBits, unsigned Idx) {2118 Res = GetKB(Idx);2119 EXPECT_EQ(64u, Res.getBitWidth());2120 EXPECT_EQ(NumBits - 1, Res.Zero.countr_one());2121 EXPECT_EQ(64u, Res.One.countr_zero());2122 EXPECT_EQ(Align(1ull << (NumBits - 1)), Info.computeKnownAlignment(Copies[Idx]));2123 };2124 2125 const unsigned NumSetupCopies = 5;2126 CheckBits(1, NumSetupCopies);2127 CheckBits(2, NumSetupCopies + 1);2128 CheckBits(3, NumSetupCopies + 2);2129 CheckBits(4, NumSetupCopies + 3);2130 CheckBits(5, NumSetupCopies + 4);2131}2132 2133TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {2134 StringRef MIRString = R"(2135 %ptr:_(p0) = G_IMPLICIT_DEF2136 %ld0:_(s32) = G_LOAD %ptr(p0) :: (load (s16))2137 %ld1:_(s32) = G_LOAD %ptr(p0) :: (load (s16))2138 2139 %add:_(s32), %overflow:_(s32) = G_UADDO %ld0, %ld12140 %copy_overflow:_(s32) = COPY %overflow2141)";2142 2143 setUp(MIRString);2144 if (!TM)2145 GTEST_SKIP();2146 2147 Register CopyOverflow = Copies[Copies.size() - 1];2148 GISelValueTracking Info(*MF);2149 KnownBits Res = Info.getKnownBits(CopyOverflow);2150 EXPECT_EQ(0u, Res.One.getZExtValue());2151 EXPECT_EQ(31u, Res.Zero.countl_one());2152}2153