1551 lines · cpp
1//===- KnownBitsTest.cpp -------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "GISelMITest.h"10#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"11#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"12 13TEST_F(AArch64GISelMITest, TestKnownBitsBuildVector) {14 StringRef MIRString = R"(15 %ptr:_(p0) = G_IMPLICIT_DEF16 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))17 %mask0:_(s8) = G_CONSTANT i8 2418 %mask1:_(s8) = G_CONSTANT i8 22419 %tmp0:_(s8) = G_AND %unknown, %mask020 %val0:_(s8) = G_OR %tmp0, %mask121 %mask2:_(s8) = G_CONSTANT i8 14622 %mask3:_(s8) = G_CONSTANT i8 3623 %tmp1:_(s8) = G_AND %unknown, %mask224 %val1:_(s8) = G_OR %tmp1, %mask325 %vector:_(<2 x s8>) = G_BUILD_VECTOR %val0, %val126 %copy_vector:_(<2 x s8>) = COPY %vector27)";28 29 setUp(MIRString);30 if (!TM)31 GTEST_SKIP();32 33 Register CopyReg = Copies[Copies.size() - 1];34 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);35 Register SrcReg = FinalCopy->getOperand(1).getReg();36 GISelValueTracking Info(*MF);37 KnownBits Res = Info.getKnownBits(SrcReg);38 // BuildVector KnownBits takes common bits of all elements.39 // 111??00040 // common ?01?01?041 // = ??1????042 EXPECT_EQ(0x20u, Res.One.getZExtValue());43 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());44}45 46// Vector KnownBits track bits that are common for all vector scalar elements.47// For tests below KnownBits analysis is same as for scalar/pointer types, tests48// are mostly copied from KnownBitsTest.cpp using splat vectors and have the49// same result.50 51TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHI) {52 StringRef MIRString = R"(53 bb.10:54 %10:_(s8) = G_CONSTANT i8 355 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)56 %12:_(s1) = G_IMPLICIT_DEF57 G_BRCOND %12(s1), %bb.1158 G_BR %bb.1259 60 bb.11:61 %13:_(s8) = G_CONSTANT i8 262 %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8)63 G_BR %bb.1264 65 bb.12:66 %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.1167 %16:_(<2 x s8>) = COPY %1568)";69 70 setUp(MIRString);71 if (!TM)72 GTEST_SKIP();73 74 Register CopyReg = Copies[Copies.size() - 1];75 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);76 Register SrcReg = FinalCopy->getOperand(1).getReg();77 Register DstReg = FinalCopy->getOperand(0).getReg();78 GISelValueTracking Info(*MF);79 KnownBits Res = Info.getKnownBits(SrcReg);80 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());81 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());82 83 KnownBits Res2 = Info.getKnownBits(DstReg);84 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());85 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());86}87 88TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIToNonGenericReg) {89 StringRef MIRString = R"(90 bb.10:91 %10:gpr32 = MOVi32imm 77192 %11:_(s1) = G_IMPLICIT_DEF93 G_BRCOND %11(s1), %bb.1194 G_BR %bb.1295 96 bb.11:97 %12:_(s16) = G_CONSTANT i16 298 %13:_(<2 x s16>) = G_BUILD_VECTOR %12:_(s16), %12:_(s16)99 G_BR %bb.12100 101 bb.12:102 %15:_(<2 x s16>) = PHI %10, %bb.10, %13(<2 x s16>), %bb.11103 %16:_(<2 x s16>) = COPY %15104)";105 106 setUp(MIRString);107 if (!TM)108 GTEST_SKIP();109 110 Register CopyReg = Copies[Copies.size() - 1];111 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);112 Register SrcReg = FinalCopy->getOperand(1).getReg();113 Register DstReg = FinalCopy->getOperand(0).getReg();114 GISelValueTracking Info(*MF);115 KnownBits Res = Info.getKnownBits(SrcReg);116 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());117 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());118 119 KnownBits Res2 = Info.getKnownBits(DstReg);120 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());121 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());122}123 124TEST_F(AArch64GISelMITest, TestKnownBitsVectorUnknownPHI) {125 StringRef MIRString = R"(126 bb.10:127 %10:_(<2 x s32>) = G_BITCAST %0128 %11:_(s1) = G_IMPLICIT_DEF129 G_BRCOND %11(s1), %bb.11130 G_BR %bb.12131 132 bb.11:133 %12:_(s32) = G_CONSTANT i32 2134 %13:_(<2 x s32>) = G_BUILD_VECTOR %12:_(s32), %12:_(s32)135 G_BR %bb.12136 137 bb.12:138 %14:_(<2 x s32>) = PHI %10(<2 x s32>), %bb.10, %13(<2 x s32>), %bb.11139 %15:_(<2 x s32>) = COPY %14140)";141 142 setUp(MIRString);143 if (!TM)144 GTEST_SKIP();145 146 Register CopyReg = Copies[Copies.size() - 1];147 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);148 Register SrcReg = FinalCopy->getOperand(1).getReg();149 Register DstReg = FinalCopy->getOperand(0).getReg();150 GISelValueTracking Info(*MF);151 KnownBits Res = Info.getKnownBits(SrcReg);152 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());153 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());154 155 KnownBits Res2 = Info.getKnownBits(DstReg);156 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());157 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());158}159 160TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIWithLoop) {161 StringRef MIRString = R"(162 bb.10:163 %10:_(s8) = G_CONSTANT i8 3164 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)165 %12:_(s1) = G_IMPLICIT_DEF166 G_BRCOND %12(s1), %bb.11167 G_BR %bb.12168 169 bb.11:170 %13:_(s8) = G_CONSTANT i8 2171 %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8)172 G_BR %bb.12173 174 bb.12:175 %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11, %16(<2 x s8>), %bb.12176 %16:_(<2 x s8>) = COPY %15177 G_BR %bb.12178)";179 180 setUp(MIRString);181 if (!TM)182 GTEST_SKIP();183 184 Register CopyReg = Copies[Copies.size() - 1];185 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);186 Register SrcReg = FinalCopy->getOperand(1).getReg();187 Register DstReg = FinalCopy->getOperand(0).getReg();188 GISelValueTracking Info(*MF);189 KnownBits Res = Info.getKnownBits(SrcReg);190 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());191 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());192 193 KnownBits Res2 = Info.getKnownBits(DstReg);194 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());195 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());196}197 198TEST_F(AArch64GISelMITest, TestKnownBitsVectorDecreasingCstPHIWithLoop) {199 StringRef MIRString = R"(200 bb.10:201 %10:_(s8) = G_CONSTANT i8 5202 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)203 %12:_(s8) = G_CONSTANT i8 1204 %16:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %12:_(s8)205 206 bb.12:207 %13:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.12208 %14:_(<2 x s8>) = G_LSHR %13, %16209 %15:_(<2 x s8>) = COPY %14210 G_BR %bb.12211)";212 213 setUp(MIRString);214 if (!TM)215 GTEST_SKIP();216 Register CopyReg = Copies[Copies.size() - 1];217 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);218 Register SrcReg = FinalCopy->getOperand(1).getReg();219 Register DstReg = FinalCopy->getOperand(0).getReg();220 GISelValueTracking Info(*MF, /*MaxDepth=*/24);221 KnownBits Res = Info.getKnownBits(SrcReg);222 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());223 EXPECT_EQ((uint64_t)0xFC, Res.Zero.getZExtValue());224 225 KnownBits Res2 = Info.getKnownBits(DstReg);226 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());227 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());228}229 230TEST_F(AArch64GISelMITest, TestKnownBitsVectorAND) {231 StringRef MIRString = R"(232 %ptr:_(p0) = G_IMPLICIT_DEF233 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))234 %mask0:_(s8) = G_CONSTANT i8 52235 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0236 %mask1:_(s8) = G_CONSTANT i8 10237 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1238 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat239 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat240 %mask2:_(s8) = G_CONSTANT i8 32241 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2242 %mask3:_(s8) = G_CONSTANT i8 24243 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3244 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat245 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat246 %and:_(<2 x s8>) = G_AND %val0, %val1247 %copy_and:_(<2 x s8>) = COPY %and248)";249 250 setUp(MIRString);251 if (!TM)252 GTEST_SKIP();253 254 Register CopyReg = Copies[Copies.size() - 1];255 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);256 Register SrcReg = FinalCopy->getOperand(1).getReg();257 GISelValueTracking Info(*MF);258 KnownBits Res = Info.getKnownBits(SrcReg);259 EXPECT_EQ(0x08u, Res.One.getZExtValue());260 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());261}262 263TEST_F(AArch64GISelMITest, TestKnownBitsVectorOR) {264 StringRef MIRString = R"(265 %ptr:_(p0) = G_IMPLICIT_DEF266 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))267 %mask0:_(s8) = G_CONSTANT i8 52268 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0269 %mask1:_(s8) = G_CONSTANT i8 10270 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1271 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat272 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat273 %mask2:_(s8) = G_CONSTANT i8 32274 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2275 %mask3:_(s8) = G_CONSTANT i8 24276 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3277 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat278 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat279 %or:_(<2 x s8>) = G_OR %val0, %val1280 %copy_or:_(<2 x s8>) = COPY %or281)";282 283 setUp(MIRString);284 if (!TM)285 GTEST_SKIP();286 287 Register CopyReg = Copies[Copies.size() - 1];288 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);289 Register SrcReg = FinalCopy->getOperand(1).getReg();290 GISelValueTracking Info(*MF);291 KnownBits Res = Info.getKnownBits(SrcReg);292 EXPECT_EQ(0x1Au, Res.One.getZExtValue());293 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());294}295 296TEST_F(AArch64GISelMITest, TestKnownBitsVectorXOR) {297 StringRef MIRString = R"(298 %ptr:_(p0) = G_IMPLICIT_DEF299 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))300 %mask0:_(s8) = G_CONSTANT i8 52301 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0302 %mask1:_(s8) = G_CONSTANT i8 10303 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1304 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat305 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat306 %mask2:_(s8) = G_CONSTANT i8 32307 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2308 %mask3:_(s8) = G_CONSTANT i8 24309 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3310 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat311 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat312 %xor:_(<2 x s8>) = G_XOR %val0, %val1313 %copy_xor:_(<2 x s8>) = COPY %xor314)";315 316 setUp(MIRString);317 if (!TM)318 GTEST_SKIP();319 320 Register CopyReg = Copies[Copies.size() - 1];321 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);322 Register SrcReg = FinalCopy->getOperand(1).getReg();323 GISelValueTracking Info(*MF);324 KnownBits Res = Info.getKnownBits(SrcReg);325 EXPECT_EQ(0x02u, Res.One.getZExtValue());326 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());327}328 329TEST_F(AArch64GISelMITest, TestKnownBitsVectorXORConstant) {330 StringRef MIRString = R"(331 %3:_(s8) = G_CONSTANT i8 4332 %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8)333 %5:_(s8) = G_CONSTANT i8 7334 %6:_(<2 x s8>) = G_BUILD_VECTOR %5:_(s8), %5:_(s8)335 %7:_(<2 x s8>) = G_XOR %4, %6336 %8:_(<2 x s8>) = COPY %7337 338 %9:_(s8) = G_CONSTANT i8 12339 %10:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %9:_(s8)340 %11:_(<2 x s8>) = G_XOR %10, %6341 %12:_(<2 x s8>) = COPY %11342)";343 344 setUp(MIRString);345 if (!TM)346 GTEST_SKIP();347 348 GISelValueTracking Info(*MF);349 Register CopySplatReg = Copies[Copies.size() - 2];350 MachineInstr *FinalSplatCopy = MRI->getVRegDef(CopySplatReg);351 Register SrcSplatReg = FinalSplatCopy->getOperand(1).getReg();352 KnownBits ResNonSplat = Info.getKnownBits(SrcSplatReg);353 EXPECT_EQ(3u, ResNonSplat.One.getZExtValue());354 EXPECT_EQ(252u, ResNonSplat.Zero.getZExtValue());355 356 Register CopyNonSplatReg = Copies[Copies.size() - 1];357 MachineInstr *FinalNonSplatCopy = MRI->getVRegDef(CopyNonSplatReg);358 Register SrcNonSplatReg = FinalNonSplatCopy->getOperand(1).getReg();359 KnownBits ResSplat = Info.getKnownBits(SrcNonSplatReg);360 EXPECT_EQ(3u, ResSplat.One.getZExtValue());361 EXPECT_EQ(244u, ResSplat.Zero.getZExtValue());362}363 364TEST_F(AArch64GISelMITest, TestKnownBitsVectorASHR) {365 StringRef MIRString = R"(366 %ptr:_(p0) = G_IMPLICIT_DEF367 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))368 %mask0:_(s8) = G_CONSTANT i8 38369 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0370 %mask1:_(s8) = G_CONSTANT i8 202371 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1372 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat373 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat374 %cst0:_(s8) = G_CONSTANT i8 2375 %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0376 %ashr0:_(<2 x s8>) = G_ASHR %val0, %cst0_splat377 %copy_ashr0:_(<2 x s8>) = COPY %ashr0378 379 %mask2:_(s8) = G_CONSTANT i8 204380 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2381 %mask3:_(s8) = G_CONSTANT i8 18382 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3383 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat384 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat385 %ashr1:_(<2 x s8>) = G_ASHR %val1, %cst0_splat386 %copy_ashr1:_(<2 x s8>) = COPY %ashr1387)";388 389 setUp(MIRString);390 if (!TM)391 GTEST_SKIP();392 393 Register CopyReg0 = Copies[Copies.size() - 2];394 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);395 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();396 GISelValueTracking Info(*MF);397 KnownBits Res0 = Info.getKnownBits(SrcReg0);398 EXPECT_EQ(0xF2u, Res0.One.getZExtValue());399 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());400 401 Register CopyReg1 = Copies[Copies.size() - 1];402 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);403 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();404 KnownBits Res1 = Info.getKnownBits(SrcReg1);405 EXPECT_EQ(0x04u, Res1.One.getZExtValue());406 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());407}408 409TEST_F(AArch64GISelMITest, TestKnownBitsVectorLSHR) {410 StringRef MIRString = R"(411 %ptr:_(p0) = G_IMPLICIT_DEF412 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))413 %mask0:_(s8) = G_CONSTANT i8 38414 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0415 %mask1:_(s8) = G_CONSTANT i8 202416 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1417 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat418 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat419 %cst0:_(s8) = G_CONSTANT i8 2420 %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0421 %lshr0:_(<2 x s8>) = G_LSHR %val0, %cst0_splat422 %copy_lshr0:_(<2 x s8>) = COPY %lshr0423 424 %mask2:_(s8) = G_CONSTANT i8 204425 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2426 %mask3:_(s8) = G_CONSTANT i8 18427 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3428 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat429 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat430 %lshr1:_(<2 x s8>) = G_LSHR %val1, %cst0_splat431 %copy_lshr1:_(<2 x s8>) = COPY %lshr1432)";433 434 setUp(MIRString);435 if (!TM)436 GTEST_SKIP();437 438 Register CopyReg0 = Copies[Copies.size() - 2];439 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);440 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();441 GISelValueTracking Info(*MF);442 KnownBits Res0 = Info.getKnownBits(SrcReg0);443 EXPECT_EQ(0x32u, Res0.One.getZExtValue());444 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());445 446 Register CopyReg1 = Copies[Copies.size() - 1];447 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);448 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();449 KnownBits Res1 = Info.getKnownBits(SrcReg1);450 EXPECT_EQ(0x04u, Res1.One.getZExtValue());451 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());452}453 454TEST_F(AArch64GISelMITest, TestKnownBitsVectorSHL) {455 StringRef MIRString = R"(456 %ptr:_(p0) = G_IMPLICIT_DEF457 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))458 %mask0:_(s8) = G_CONSTANT i8 51459 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0460 %mask1:_(s8) = G_CONSTANT i8 72461 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1462 %tmp:_(<2 x s8>) = G_AND %unknown, %mask0_splat463 %val:_(<2 x s8>) = G_OR %tmp, %mask1_splat464 %cst:_(s8) = G_CONSTANT i8 3465 %cst_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst, %cst466 %shl:_(<2 x s8>) = G_SHL %val, %cst_splat467 %copy_shl:_(<2 x s8>) = COPY %shl468)";469 470 setUp(MIRString);471 if (!TM)472 GTEST_SKIP();473 474 Register CopyReg = Copies[Copies.size() - 1];475 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);476 Register SrcReg = FinalCopy->getOperand(1).getReg();477 GISelValueTracking Info(*MF);478 KnownBits Res = Info.getKnownBits(SrcReg);479 EXPECT_EQ(0x40u, Res.One.getZExtValue());480 EXPECT_EQ(0x27u, Res.Zero.getZExtValue());481}482 483TEST_F(AArch64GISelMITest, TestKnownBitsVectorADD) {484 StringRef MIRString = R"(485 %ptr:_(p0) = G_IMPLICIT_DEF486 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))487 %mask0:_(s16) = G_CONSTANT i16 4642488 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0489 %mask1:_(s16) = G_CONSTANT i16 9536490 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1491 %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat492 %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat493 %mask2:_(s16) = G_CONSTANT i16 4096494 %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2495 %mask3:_(s16) = G_CONSTANT i16 371496 %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3497 %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat498 %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat499 %add:_(<2 x s16>) = G_ADD %val0, %val1500 %copy_add:_(<2 x s16>) = COPY %add501)";502 503 setUp(MIRString);504 if (!TM)505 GTEST_SKIP();506 507 Register CopyReg = Copies[Copies.size() - 1];508 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);509 Register SrcReg = FinalCopy->getOperand(1).getReg();510 GISelValueTracking Info(*MF);511 KnownBits Res = Info.getKnownBits(SrcReg);512 EXPECT_EQ(0x0091u, Res.One.getZExtValue());513 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());514}515 516TEST_F(AArch64GISelMITest, TestKnownBitsVectorSUB) {517 StringRef MIRString = R"(518 %ptr:_(p0) = G_IMPLICIT_DEF519 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))520 %mask0:_(s16) = G_CONSTANT i16 4642521 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0522 %mask1:_(s16) = G_CONSTANT i16 9536523 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1524 %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat525 %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat526 %mask2:_(s16) = G_CONSTANT i16 4096527 %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2528 %mask3:_(s16) = G_CONSTANT i16 371529 %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3530 %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat531 %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat532 %sub:_(<2 x s16>) = G_SUB %val0, %val1533 %copy_sub:_(<2 x s16>) = COPY %sub534)";535 536 setUp(MIRString);537 if (!TM)538 GTEST_SKIP();539 540 Register CopyReg = Copies[Copies.size() - 1];541 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);542 Register SrcReg = FinalCopy->getOperand(1).getReg();543 GISelValueTracking Info(*MF);544 KnownBits Res = Info.getKnownBits(SrcReg);545 EXPECT_EQ(0x01CDu, Res.One.getZExtValue());546 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());547}548 549TEST_F(AArch64GISelMITest, TestKnownBitsVectorMUL) {550 StringRef MIRString = R"(551 %ptr:_(p0) = G_IMPLICIT_DEF552 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))553 %mask0:_(s16) = G_CONSTANT i16 4554 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0555 %mask1:_(s16) = G_CONSTANT i16 18556 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1557 %tmp:_(<2 x s16>) = G_AND %unknown, %mask0_splat558 %val0:_(<2 x s16>) = G_OR %tmp, %mask1_splat559 %cst:_(s16) = G_CONSTANT i16 12560 %cst_splat:_(<2 x s16>) = G_BUILD_VECTOR %cst, %cst561 %mul:_(<2 x s16>) = G_MUL %val0, %cst_splat562 %copy_mul:_(<2 x s16>) = COPY %mul563)";564 565 setUp(MIRString);566 if (!TM)567 GTEST_SKIP();568 569 Register CopyReg = Copies[Copies.size() - 1];570 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);571 Register SrcReg = FinalCopy->getOperand(1).getReg();572 GISelValueTracking Info(*MF);573 KnownBits Res = Info.getKnownBits(SrcReg);574 EXPECT_EQ(0x0008u, Res.One.getZExtValue());575 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());576}577 578TEST_F(AArch64GISelMITest, TestKnownBitsVectorSelect) {579 StringRef MIRString = R"(580 %ptr:_(p0) = G_IMPLICIT_DEF581 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))582 %mask0:_(s8) = G_CONSTANT i8 24583 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0584 %mask1:_(s8) = G_CONSTANT i8 224585 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1586 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat587 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat588 %mask2:_(s8) = G_CONSTANT i8 146589 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2590 %mask3:_(s8) = G_CONSTANT i8 36591 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3592 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat593 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat594 %cond:_(s1) = G_CONSTANT i1 false595 %cond_splat:_(<2 x s1>) = G_BUILD_VECTOR %cond, %cond596 %select:_(<2 x s8>) = G_SELECT %cond_splat, %val0, %val1597 %copy_select:_(<2 x s8>) = COPY %select598)";599 600 setUp(MIRString);601 if (!TM)602 GTEST_SKIP();603 604 Register CopyReg = Copies[Copies.size() - 1];605 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);606 Register SrcReg = FinalCopy->getOperand(1).getReg();607 GISelValueTracking Info(*MF);608 KnownBits Res = Info.getKnownBits(SrcReg);609 EXPECT_EQ(0x20u, Res.One.getZExtValue());610 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());611}612 613TEST_F(AArch64GISelMITest, TestVectorSignBitIsZero) {614 setUp();615 if (!TM)616 GTEST_SKIP();617 618 const LLT V2S32 = LLT::fixed_vector(2, 32);619 // Vector buildConstant makes splat G_BUILD_VECTOR instruction.620 auto SignBit = B.buildConstant(V2S32, 0x80000000);621 auto Zero = B.buildConstant(V2S32, 0);622 623 const LLT S32 = LLT::scalar(32);624 auto NonSplat =625 B.buildBuildVector(V2S32, {B.buildConstant(S32, 1).getReg(0),626 B.buildConstant(S32, 2).getReg(0)});627 auto NonSplat2 =628 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0),629 B.buildConstant(S32, 0x80000004).getReg(0)});630 // signBitIsZero is true for elt 0 and false for elt 1 GISelValueTracking631 // takes common bits so this is false.632 auto NonSplat3 =633 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0),634 B.buildConstant(S32, 0x8).getReg(0)});635 GISelValueTracking KnownBits(*MF);636 637 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));638 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));639 EXPECT_TRUE(KnownBits.signBitIsZero(NonSplat.getReg(0)));640 EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat2.getReg(0)));641 EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat3.getReg(0)));642}643 644TEST_F(AArch64GISelMITest, TestVectorNumSignBitsConstant) {645 StringRef MIRString = R"(646 %3:_(s8) = G_CONSTANT i8 1647 %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8)648 %5:_(<2 x s8>) = COPY %4649 650 %6:_(s8) = G_CONSTANT i8 -1651 %7:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %6:_(s8)652 %8:_(<2 x s8>) = COPY %7653 654 %9:_(s8) = G_CONSTANT i8 127655 %10:_(<2 x s8>) = G_BUILD_VECTOR %9:_(s8), %9:_(s8)656 %11:_(<2 x s8>) = COPY %10657 658 %12:_(s8) = G_CONSTANT i8 32659 %13:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %12:_(s8)660 %14:_(<2 x s8>) = COPY %13661 662 %15:_(s8) = G_CONSTANT i8 -32663 %16:_(<2 x s8>) = G_BUILD_VECTOR %15:_(s8), %15:_(s8)664 %17:_(<2 x s8>) = COPY %16665 666 %18:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %15:_(s8)667 %19:_(<2 x s8>) = COPY %18668 669 %20:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %15:_(s8)670 %21:_(<2 x s8>) = COPY %20671)";672 673 setUp(MIRString);674 if (!TM)675 GTEST_SKIP();676 677 Register CopyReg1 = Copies[Copies.size() - 7];678 Register CopyRegNeg1 = Copies[Copies.size() - 6];679 Register CopyReg127 = Copies[Copies.size() - 5];680 Register CopyReg32 = Copies[Copies.size() - 4];681 Register CopyRegNeg32 = Copies[Copies.size() - 3];682 Register NonSplatSameSign = Copies[Copies.size() - 2];683 Register NonSplatDifferentSign = Copies[Copies.size() - 1];684 685 GISelValueTracking Info(*MF);686 // If it is known that all elts have same sign looks at common bits and687 // effectively returns smallest NumSignBits of all the elts. Otherwise returns688 // default value 1.689 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));690 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));691 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));692 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));693 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));694 EXPECT_EQ(3u, Info.computeNumSignBits(NonSplatSameSign));695 EXPECT_EQ(2u, Info.computeNumSignBits(NonSplatDifferentSign));696}697 698TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSext) {699 StringRef MIRString = R"(700 %3:_(p0) = G_IMPLICIT_DEF701 %4:_(<2 x s8>) = G_LOAD %3 :: (load (<2 x s8>))702 %5:_(<2 x s32>) = G_SEXT %4703 %6:_(<2 x s32>) = COPY %5704 705 %7:_(s8) = G_CONSTANT i8 -1706 %8:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %7:_(s8)707 %9:_(<2 x s32>) = G_SEXT %8708 %10:_(<2 x s32>) = COPY %9709 710 %11:_(s8) = G_CONSTANT i8 -10711 %12:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %11:_(s8)712 %13:_(<2 x s32>) = G_SEXT %12713 %14:_(<2 x s32>) = COPY %13714)";715 716 setUp(MIRString);717 if (!TM)718 GTEST_SKIP();719 Register CopySextLoad = Copies[Copies.size() - 3];720 Register CopySextNeg1 = Copies[Copies.size() - 2];721 Register CopySextNonSplat = Copies[Copies.size() - 1];722 723 GISelValueTracking Info(*MF);724 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));725 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));726 EXPECT_EQ(28u, Info.computeNumSignBits(CopySextNonSplat));727}728 729TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSextInReg) {730 StringRef MIRString = R"(731 %ptr:_(p0) = G_IMPLICIT_DEF732 %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>))733 734 %inreg7:_(<2 x s32>) = G_SEXT_INREG %load2x4, 7735 %copy_inreg7:_(<2 x s32>) = COPY %inreg7736 737 %inreg8:_(<2 x s32>) = G_SEXT_INREG %load2x4, 8738 %copy_inreg8:_(<2 x s32>) = COPY %inreg8739 740 %inreg9:_(<2 x s32>) = G_SEXT_INREG %load2x4, 9741 %copy_inreg9:_(<2 x s32>) = COPY %inreg9742 743 %inreg31:_(<2 x s32>) = G_SEXT_INREG %load2x4, 31744 %copy_inreg31:_(<2 x s32>) = COPY %inreg31745 746 %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>))747 %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1748 749 %inreg6_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 6750 %copy_inreg6_sext:_(<2 x s32>) = COPY %inreg6_sext751 752 %inreg7_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 7753 %copy_inreg7_sext:_(<2 x s32>) = COPY %inreg7_sext754 755 %inreg8_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 8756 %copy_inreg8_sext:_(<2 x s32>) = COPY %inreg8_sext757 758 %inreg9_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 9759 %copy_inreg9_sext:_(<2 x s32>) = COPY %inreg9_sext760 761 %inreg31_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 31762 %copy_inreg31_sext:_(<2 x s32>) = COPY %inreg31_sext763)";764 765 setUp(MIRString);766 if (!TM)767 GTEST_SKIP();768 769 Register CopyInReg7 = Copies[Copies.size() - 9];770 Register CopyInReg8 = Copies[Copies.size() - 8];771 Register CopyInReg9 = Copies[Copies.size() - 7];772 Register CopyInReg31 = Copies[Copies.size() - 6];773 774 Register CopyInReg6Sext = Copies[Copies.size() - 5];775 Register CopyInReg7Sext = Copies[Copies.size() - 4];776 Register CopyInReg8Sext = Copies[Copies.size() - 3];777 Register CopyInReg9Sext = Copies[Copies.size() - 2];778 Register CopyInReg31Sext = Copies[Copies.size() - 1];779 780 GISelValueTracking Info(*MF);781 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));782 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));783 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));784 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));785 786 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));787 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));788 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));789 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));790 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));791}792 793TEST_F(AArch64GISelMITest, TestNumSignBitsVectorAssertSext) {794 StringRef MIRString = R"(795 %ptr:_(p0) = G_IMPLICIT_DEF796 %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>))797 798 %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 1799 %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext1800 801 %assert_sext7:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 7802 %copy_assert_sext7:_(<2 x s32>) = COPY %assert_sext7803 804 %assert_sext8:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 8805 %copy_assert_sext8:_(<2 x s32>) = COPY %assert_sext8806 807 %assert_sext9:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 9808 %copy_assert_sext9:_(<2 x s32>) = COPY %assert_sext9809 810 %assert_sext31:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 31811 %copy_assert_sext31:_(<2 x s32>) = COPY %assert_sext31812 813 %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>))814 %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1815 816 %assert_sext6_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 6817 %copy_assert_sext6_sext:_(<2 x s32>) = COPY %assert_sext6_sext818 819 %assert_sext7_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 7820 %copy_assert_sext7_sext:_(<2 x s32>) = COPY %assert_sext7_sext821 822 %assert_sext8_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 8823 %copy_assert_sext8_sext:_(<2 x s32>) = COPY %assert_sext8_sext824 825 %assert_sext9_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 9826 %copy_assert_sext9_sext:_(<2 x s32>) = COPY %assert_sext9_sext827 828 %assert_sext31_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 31829 %copy_assert_sext31_sext:_(<2 x s32>) = COPY %assert_sext31_sext830)";831 832 setUp(MIRString);833 if (!TM)834 GTEST_SKIP();835 836 Register CopyInReg1 = Copies[Copies.size() - 10];837 Register CopyInReg7 = Copies[Copies.size() - 9];838 Register CopyInReg8 = Copies[Copies.size() - 8];839 Register CopyInReg9 = Copies[Copies.size() - 7];840 Register CopyInReg31 = Copies[Copies.size() - 6];841 842 Register CopyInReg6Sext = Copies[Copies.size() - 5];843 Register CopyInReg7Sext = Copies[Copies.size() - 4];844 Register CopyInReg8Sext = Copies[Copies.size() - 3];845 Register CopyInReg9Sext = Copies[Copies.size() - 2];846 Register CopyInReg31Sext = Copies[Copies.size() - 1];847 848 GISelValueTracking Info(*MF);849 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));850 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));851 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));852 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));853 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));854 855 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));856 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));857 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));858 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));859 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));860}861 862TEST_F(AArch64GISelMITest, TestVectorNumSignBitsTrunc) {863 StringRef MIRString = R"(864 %3:_(p0) = G_IMPLICIT_DEF865 %4:_(<2 x s32>) = G_LOAD %3 :: (load (<2 x s32>))866 %5:_(<2 x s8>) = G_TRUNC %4867 %6:_(<2 x s8>) = COPY %5868 869 %7:_(s32) = G_CONSTANT i32 -1870 %8:_(<2 x s32>) = G_BUILD_VECTOR %7:_(s32), %7:_(s32)871 %9:_(<2 x s8>) = G_TRUNC %8872 %10:_(<2 x s8>) = COPY %9873 874 %11:_(s32) = G_CONSTANT i32 7875 %12:_(<2 x s32>) = G_BUILD_VECTOR %11:_(s32), %11:_(s32)876 %13:_(<2 x s8>) = G_TRUNC %12877 %14:_(<2 x s8>) = COPY %13878)";879 880 setUp(MIRString);881 if (!TM)882 GTEST_SKIP();883 884 Register CopyTruncLoad = Copies[Copies.size() - 3];885 Register CopyTruncNeg1 = Copies[Copies.size() - 2];886 Register CopyTrunc7 = Copies[Copies.size() - 1];887 888 GISelValueTracking Info(*MF);889 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));890 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));891 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));892}893 894TEST_F(AMDGPUGISelMITest, TestVectorIsKnownToBeAPowerOfTwo) {895 896 StringRef MIRString = R"(897 %zero:_(s32) = G_CONSTANT i32 0898 %zero_splat:_(<2 x s32>) = G_BUILD_VECTOR %zero:_(s32), %zero:_(s32)899 %one:_(s32) = G_CONSTANT i32 1900 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32)901 %two:_(s32) = G_CONSTANT i32 2902 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32)903 %three:_(s32) = G_CONSTANT i32 3904 %three_splat:_(<2 x s32>) = G_BUILD_VECTOR %three:_(s32), %three:_(s32)905 %five:_(s32) = G_CONSTANT i32 5906 %five_splat:_(<2 x s32>) = G_BUILD_VECTOR %five:_(s32), %five:_(s32)907 %copy_zero_splat:_(<2 x s32>) = COPY %zero_splat908 %copy_one_splat:_(<2 x s32>) = COPY %one_splat909 %copy_two_splat:_(<2 x s32>) = COPY %two_splat910 %copy_three_splat:_(<2 x s32>) = COPY %three_splat911 912 %trunc_two_splat:_(<2 x s1>) = G_TRUNC %two_splat913 %trunc_three_splat:_(<2 x s1>) = G_TRUNC %three_splat914 %trunc_five_splat:_(<2 x s1>) = G_TRUNC %five_splat915 916 %copy_trunc_two_splat:_(<2 x s1>) = COPY %trunc_two_splat917 %copy_trunc_three_splat:_(<2 x s1>) = COPY %trunc_three_splat918 %copy_trunc_five_splat:_(<2 x s1>) = COPY %trunc_five_splat919 920 %ptr:_(p1) = G_IMPLICIT_DEF921 %shift_amt:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1)922 923 %shl_1:_(<2 x s32>) = G_SHL %one_splat, %shift_amt924 %copy_shl_1:_(<2 x s32>) = COPY %shl_1925 926 %shl_2:_(<2 x s32>) = G_SHL %two_splat, %shift_amt927 %copy_shl_2:_(<2 x s32>) = COPY %shl_2928 929 %not_sign_mask:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1)930 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648931 %sign_mask_splat:_(<2 x s32>) = G_BUILD_VECTOR %sign_mask:_(s32), %sign_mask:_(s32)932 933 %lshr_not_sign_mask:_(<2 x s32>) = G_LSHR %not_sign_mask, %shift_amt934 %copy_lshr_not_sign_mask:_(<2 x s32>) = COPY %lshr_not_sign_mask935 936 %lshr_sign_mask:_(<2 x s32>) = G_LSHR %sign_mask_splat, %shift_amt937 %copy_lshr_sign_mask:_(<2 x s32>) = COPY %lshr_sign_mask938 939 %or_pow2:_(<2 x s32>) = G_OR %zero_splat, %two_splat940 %copy_or_pow2:_(<2 x s32>) = COPY %or_pow2941)";942 943 setUp(MIRString);944 if (!TM)945 GTEST_SKIP();946 947 GISelValueTracking VT(*MF);948 949 Register CopyZero = Copies[Copies.size() - 12];950 Register CopyOne = Copies[Copies.size() - 11];951 Register CopyTwo = Copies[Copies.size() - 10];952 Register CopyThree = Copies[Copies.size() - 9];953 Register CopyTruncTwo = Copies[Copies.size() - 8];954 Register CopyTruncThree = Copies[Copies.size() - 7];955 Register CopyTruncFive = Copies[Copies.size() - 6];956 957 Register CopyShl1 = Copies[Copies.size() - 5];958 Register CopyShl2 = Copies[Copies.size() - 4];959 960 Register CopyLShrNotSignMask = Copies[Copies.size() - 3];961 Register CopyLShrSignMask = Copies[Copies.size() - 2];962 Register CopyOrPow2 = Copies[Copies.size() - 1];963 964 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &VT));965 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &VT));966 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &VT));967 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &VT));968 969 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &VT));970 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &VT));971 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &VT));972 // TODO: check for vector(splat) shift amount.973 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &VT));974 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &VT));975 976 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &VT));977 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &VT));978 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &VT));979}980 981TEST_F(AArch64GISelMITest, TestVectorMetadata) {982 StringRef MIRString = R"(983 %imp:_(p0) = G_IMPLICIT_DEF984 %load:_(<2 x s8>) = G_LOAD %imp(p0) :: (load (<2 x s8>))985 %ext:_(<2 x s32>) = G_ZEXT %load(<2 x s8>)986 %cst_elt:_(s32) = G_CONSTANT i32 1987 %cst:_(<2 x s32>) = G_BUILD_VECTOR %cst_elt:_(s32), %cst_elt:_(s32)988 %and:_(<2 x s32>) = G_AND %ext, %cst989 %copy:_(<2 x s32>) = COPY %and(<2 x s32>)990)";991 992 setUp(MIRString);993 if (!TM)994 GTEST_SKIP();995 996 Register CopyReg = Copies[Copies.size() - 1];997 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);998 Register SrcReg = FinalCopy->getOperand(1).getReg();999 1000 MachineInstr *And = MRI->getVRegDef(SrcReg);1001 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());1002 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());1003 IntegerType *Int8Ty = Type::getInt8Ty(Context);1004 1005 Metadata *LowAndHigh[] = {1006 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),1007 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};1008 auto *NewMDNode = MDNode::get(Context, LowAndHigh);1009 const MachineMemOperand *OldMMO = *Load->memoperands_begin();1010 MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(),1011 OldMMO->getMemoryType(), OldMMO->getAlign(),1012 OldMMO->getAAInfo(), NewMDNode);1013 MachineIRBuilder MIB(*Load);1014 MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO);1015 Load->eraseFromParent();1016 1017 GISelValueTracking Info(*MF);1018 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());1019 1020 EXPECT_TRUE(Res.One.isZero());1021 1022 APInt Mask(Res.getBitWidth(), 1);1023 Mask.flipAllBits();1024 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());1025}1026 1027TEST_F(AArch64GISelMITest, TestVectorKnownBitsExt) {1028 StringRef MIRString = R"(1029 %c1:_(s16) = G_CONSTANT i16 11030 %c1_splat:_(<2 x s16>) = G_BUILD_VECTOR %c1:_(s16), %c1:_(s16)1031 %x:_(<2 x s16>) = G_IMPLICIT_DEF1032 %y:_(<2 x s16>) = G_AND %x, %c1_splat1033 %anyext:_(<2 x s32>) = G_ANYEXT %y(<2 x s16>)1034 %r1:_(<2 x s32>) = COPY %anyext1035 %zext:_(<2 x s32>) = G_ZEXT %y(<2 x s16>)1036 %r2:_(<2 x s32>) = COPY %zext1037 %sext:_(<2 x s32>) = G_SEXT %y(<2 x s16>)1038 %r3:_(<2 x s32>) = COPY %sext1039)";1040 1041 setUp(MIRString);1042 if (!TM)1043 GTEST_SKIP();1044 Register CopyRegAny = Copies[Copies.size() - 3];1045 Register CopyRegZ = Copies[Copies.size() - 2];1046 Register CopyRegS = Copies[Copies.size() - 1];1047 1048 GISelValueTracking Info(*MF);1049 MachineInstr *Copy;1050 Register SrcReg;1051 KnownBits Res;1052 1053 Copy = MRI->getVRegDef(CopyRegAny);1054 SrcReg = Copy->getOperand(1).getReg();1055 Res = Info.getKnownBits(SrcReg);1056 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1057 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1058 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());1059 1060 Copy = MRI->getVRegDef(CopyRegZ);1061 SrcReg = Copy->getOperand(1).getReg();1062 Res = Info.getKnownBits(SrcReg);1063 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1064 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1065 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());1066 1067 Copy = MRI->getVRegDef(CopyRegS);1068 SrcReg = Copy->getOperand(1).getReg();1069 Res = Info.getKnownBits(SrcReg);1070 EXPECT_EQ((uint64_t)32, Res.getBitWidth());1071 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());1072 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());1073}1074 1075TEST_F(AArch64GISelMITest, TestKnownBitsVectorSextInReg) {1076 StringRef MIRString = R"(1077 ; 000...00011078 %one:_(s32) = G_CONSTANT i32 11079 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32)1080 1081 ; 000...00101082 %two:_(s32) = G_CONSTANT i32 21083 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32)1084 1085 ; 000...10101086 %ten:_(s32) = G_CONSTANT i32 101087 %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten:_(s32), %ten:_(s32)1088 1089 ; ???...????1090 %x0:_(<2 x s32>) = COPY $x01091 1092 ; ???...?1?1093 %or:_(<2 x s32>) = G_OR %x0, %two_splat1094 1095 ; All bits are known.1096 %inreg1:_(<2 x s32>) = G_SEXT_INREG %one_splat, 11097 %copy_inreg1:_(<2 x s32>) = COPY %inreg11098 1099 ; All bits unknown1100 %inreg2:_(<2 x s32>) = G_SEXT_INREG %or, 11101 %copy_inreg2:_(<2 x s32>) = COPY %inreg21102 1103 ; Extending from the only (known) set bit1104 ; 111...11?1105 %inreg3:_(<2 x s32>) = G_SEXT_INREG %or, 21106 %copy_inreg3:_(<2 x s32>) = COPY %inreg31107 1108 ; Extending from a known set bit, overwriting all of the high set bits.1109 ; 111...11101110 %inreg4:_(<2 x s32>) = G_SEXT_INREG %ten_splat, 21111 %copy_inreg4:_(<2 x s32>) = COPY %inreg41112 1113)";1114 setUp(MIRString);1115 if (!TM)1116 GTEST_SKIP();1117 GISelValueTracking Info(*MF);1118 KnownBits Res;1119 auto GetKB = [&](unsigned Idx) {1120 Register CopyReg = Copies[Idx];1121 auto *Copy = MRI->getVRegDef(CopyReg);1122 return Info.getKnownBits(Copy->getOperand(1).getReg());1123 };1124 1125 Res = GetKB(Copies.size() - 4);1126 EXPECT_EQ(32u, Res.getBitWidth());1127 EXPECT_TRUE(Res.isAllOnes());1128 1129 Res = GetKB(Copies.size() - 3);1130 EXPECT_EQ(32u, Res.getBitWidth());1131 EXPECT_TRUE(Res.isUnknown());1132 1133 Res = GetKB(Copies.size() - 2);1134 EXPECT_EQ(32u, Res.getBitWidth());1135 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1136 EXPECT_EQ(0u, Res.Zero.getZExtValue());1137 1138 Res = GetKB(Copies.size() - 1);1139 EXPECT_EQ(32u, Res.getBitWidth());1140 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1141 EXPECT_EQ(1u, Res.Zero.getZExtValue());1142}1143 1144TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertSext) {1145 StringRef MIRString = R"(1146 ; 000...00011147 %one:_(s32) = G_CONSTANT i32 11148 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one, %one1149 1150 ; 000...00101151 %two:_(s32) = G_CONSTANT i32 21152 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two, %two1153 1154 ; 000...10101155 %ten:_(s32) = G_CONSTANT i32 101156 %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten, %ten1157 1158 ; ???...????1159 %x0:_(<2 x s32>) = COPY $x01160 1161 ; ???...?1?1162 %or:_(<2 x s32>) = G_OR %x0, %two_splat1163 1164 ; All bits are known.1165 %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %one_splat, 11166 %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext11167 1168 ; All bits unknown1169 %assert_sext2:_(<2 x s32>) = G_ASSERT_SEXT %or, 11170 %copy_assert_sext2:_(<2 x s32>) = COPY %assert_sext21171 1172 ; Extending from the only (known) set bit1173 ; 111...11?1174 %assert_sext3:_(<2 x s32>) = G_ASSERT_SEXT %or, 21175 %copy_assert_sext3:_(<2 x s32>) = COPY %assert_sext31176 1177 ; Extending from a known set bit, overwriting all of the high set bits.1178 ; 111...11101179 %assert_sext4:_(<2 x s32>) = G_ASSERT_SEXT %ten_splat, 21180 %copy_assert_sext4:_(<2 x s32>) = COPY %assert_sext41181)";1182 setUp(MIRString);1183 if (!TM)1184 GTEST_SKIP();1185 GISelValueTracking Info(*MF);1186 KnownBits Res;1187 auto GetKB = [&](unsigned Idx) {1188 Register CopyReg = Copies[Idx];1189 auto *Copy = MRI->getVRegDef(CopyReg);1190 return Info.getKnownBits(Copy->getOperand(1).getReg());1191 };1192 1193 // Every bit is known to be a 1.1194 Res = GetKB(Copies.size() - 4);1195 EXPECT_EQ(32u, Res.getBitWidth());1196 EXPECT_TRUE(Res.isAllOnes());1197 1198 // All bits are unknown1199 Res = GetKB(Copies.size() - 3);1200 EXPECT_EQ(32u, Res.getBitWidth());1201 EXPECT_TRUE(Res.isUnknown());1202 1203 // Extending from the only known set bit1204 // 111...11?1205 Res = GetKB(Copies.size() - 2);1206 EXPECT_EQ(32u, Res.getBitWidth());1207 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1208 EXPECT_EQ(0u, Res.Zero.getZExtValue());1209 1210 // Extending from a known set bit, overwriting all of the high set bits.1211 // 111...11101212 Res = GetKB(Copies.size() - 1);1213 EXPECT_EQ(32u, Res.getBitWidth());1214 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());1215 EXPECT_EQ(1u, Res.Zero.getZExtValue());1216}1217 1218TEST_F(AArch64GISelMITest, TestVectorKnownBitsBSwapBitReverse) {1219 StringRef MIRString = R"(1220 %const:_(s32) = G_CONSTANT i32 2874540201221 %const_splat:_(<2 x s32>) = G_BUILD_VECTOR %const:_(s32), %const:_(s32)1222 %bswap:_(<2 x s32>) = G_BSWAP %const_splat1223 %bitreverse:_(<2 x s32>) = G_BITREVERSE %const_splat1224 %copy_bswap:_(<2 x s32>) = COPY %bswap1225 %copy_bitreverse:_(<2 x s32>) = COPY %bitreverse1226)";1227 setUp(MIRString);1228 if (!TM)1229 GTEST_SKIP();1230 1231 const uint32_t ByteSwappedVal = 0x44332211;1232 const uint32_t BitSwappedVal = 0x22cc4488;1233 1234 Register CopyBSwap = Copies[Copies.size() - 2];1235 Register CopyBitReverse = Copies[Copies.size() - 1];1236 1237 GISelValueTracking Info(*MF);1238 1239 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);1240 EXPECT_EQ(32u, BSwapKnown.getBitWidth());1241 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());1242 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());1243 1244 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);1245 EXPECT_EQ(32u, BitReverseKnown.getBitWidth());1246 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());1247 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());1248}1249 1250TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMAX) {1251 StringRef MIRString = R"(1252 %ptr:_(p0) = G_IMPLICIT_DEF1253 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))1254 %mask0:_(s8) = G_CONSTANT i8 101255 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask01256 %mask1:_(s8) = G_CONSTANT i8 11257 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask11258 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat1259 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat1260 %mask2:_(s8) = G_CONSTANT i8 31261 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask21262 %mask3:_(s8) = G_CONSTANT i8 121263 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask31264 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat1265 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat1266 %umax0:_(<2 x s8>) = G_UMAX %val0, %val11267 %copy_umax0:_(<2 x s8>) = COPY %umax01268 1269 %mask4:_(s8) = G_CONSTANT i8 141270 %mask4_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask4, %mask41271 %mask5:_(s8) = G_CONSTANT i8 21272 %mask5_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask5, %mask51273 %tmp3:_(<2 x s8>) = G_AND %unknown, %mask4_splat1274 %val3:_(<2 x s8>) = G_OR %tmp3, %mask5_splat1275 %mask6:_(s8) = G_CONSTANT i8 41276 %mask6_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask6, %mask61277 %mask7:_(s8) = G_CONSTANT i8 111278 %mask7_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask7, %mask71279 %tmp4:_(<2 x s8>) = G_AND %unknown, %mask6_splat1280 %val4:_(<2 x s8>) = G_OR %tmp4, %mask7_splat1281 %umax1:_(<2 x s8>) = G_UMAX %val3, %val41282 %copy_umax1:_(<2 x s8>) = COPY %umax11283)";1284 1285 setUp(MIRString);1286 if (!TM)1287 GTEST_SKIP();1288 1289 Register CopyReg0 = Copies[Copies.size() - 2];1290 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1291 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1292 GISelValueTracking Info(*MF);1293 KnownBits Res0 = Info.getKnownBits(SrcReg0);1294 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());1295 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());1296 1297 Register CopyReg1 = Copies[Copies.size() - 1];1298 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);1299 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();1300 KnownBits Res1 = Info.getKnownBits(SrcReg1);1301 EXPECT_EQ(0x0Au, Res1.One.getZExtValue());1302 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());1303}1304 1305TEST_F(AArch64GISelMITest, TestVectorKnownBitsUMax) {1306 StringRef MIRString = R"(1307 %val:_(<2 x s32>) = COPY $x01308 %zext:_(<2 x s64>) = G_ZEXT %val1309 %const:_(s64) = G_CONSTANT i64 -2561310 %const_splat:_(<2 x s64>) = G_BUILD_VECTOR %const:_(s64), %const:_(s64)1311 %umax:_(<2 x s64>) = G_UMAX %zext, %const_splat1312 %copy_umax:_(<2 x s64>) = COPY %umax1313)";1314 1315 setUp(MIRString);1316 if (!TM)1317 GTEST_SKIP();1318 1319 Register CopyUMax = Copies[Copies.size() - 1];1320 GISelValueTracking Info(*MF);1321 1322 KnownBits KnownUmax = Info.getKnownBits(CopyUMax);1323 EXPECT_EQ(64u, KnownUmax.getBitWidth());1324 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());1325 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());1326 1327 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());1328 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());1329}1330 1331TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMIN) {1332 StringRef MIRString = R"(1333 %ptr:_(p0) = G_IMPLICIT_DEF1334 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))1335 %mask0:_(s8) = G_CONSTANT i8 101336 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask01337 %mask1:_(s8) = G_CONSTANT i8 11338 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask11339 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat1340 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat1341 %mask2:_(s8) = G_CONSTANT i8 31342 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask21343 %mask3:_(s8) = G_CONSTANT i8 121344 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask31345 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat1346 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat1347 %umin:_(<2 x s8>) = G_UMIN %val0, %val11348 %copy_umin:_(<2 x s8>) = COPY %umin1349)";1350 1351 setUp(MIRString);1352 if (!TM)1353 GTEST_SKIP();1354 1355 Register CopyReg0 = Copies[Copies.size() - 1];1356 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1357 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1358 GISelValueTracking Info(*MF);1359 KnownBits Res0 = Info.getKnownBits(SrcReg0);1360 EXPECT_EQ(0x01u, Res0.One.getZExtValue());1361 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());1362}1363 1364TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMAX) {1365 StringRef MIRString = R"(1366 %ptr:_(p0) = G_IMPLICIT_DEF1367 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))1368 %mask0:_(s8) = G_CONSTANT i8 1281369 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask01370 %mask1:_(s8) = G_CONSTANT i8 641371 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask11372 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat1373 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat1374 %mask2:_(s8) = G_CONSTANT i8 11375 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask21376 %mask3:_(s8) = G_CONSTANT i8 1281377 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask31378 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat1379 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat1380 %smax:_(<2 x s8>) = G_SMAX %val0, %val11381 %copy_smax:_(<2 x s8>) = COPY %smax1382)";1383 1384 setUp(MIRString);1385 if (!TM)1386 GTEST_SKIP();1387 1388 Register CopyReg0 = Copies[Copies.size() - 1];1389 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1390 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1391 GISelValueTracking Info(*MF);1392 KnownBits Res0 = Info.getKnownBits(SrcReg0);1393 EXPECT_EQ(0x40u, Res0.One.getZExtValue());1394 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());1395}1396 1397TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMIN) {1398 StringRef MIRString = R"(1399 %ptr:_(p0) = G_IMPLICIT_DEF1400 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))1401 %mask0:_(s8) = G_CONSTANT i8 1281402 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask01403 %mask1:_(s8) = G_CONSTANT i8 641404 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask11405 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat1406 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat1407 %mask2:_(s8) = G_CONSTANT i8 11408 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask21409 %mask3:_(s8) = G_CONSTANT i8 1281410 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask31411 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat1412 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat1413 %smin:_(<2 x s8>) = G_SMIN %val0, %val11414 %copy_smin:_(<2 x s8>) = COPY %smin1415)";1416 1417 setUp(MIRString);1418 if (!TM)1419 GTEST_SKIP();1420 1421 Register CopyReg0 = Copies[Copies.size() - 1];1422 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);1423 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();1424 GISelValueTracking Info(*MF);1425 KnownBits Res0 = Info.getKnownBits(SrcReg0);1426 EXPECT_EQ(0x80u, Res0.One.getZExtValue());1427 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());1428}1429 1430TEST_F(AArch64GISelMITest, TestVectorInvalidQueries) {1431 StringRef MIRString = R"(1432 %src:_(<2 x s32>) = COPY $x01433 %thirty2:_(s32) = G_CONSTANT i32 321434 %thirty2_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty2:_(s32), %thirty2:_(s32)1435 %equalSized:_(<2 x s32>) = G_SHL %src, %thirty2_splat1436 %copy1:_(<2 x s32>) = COPY %equalSized1437 %thirty3:_(s32) = G_CONSTANT i32 331438 %thirty3_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty3:_(s32), %thirty3:_(s32)1439 %biggerSized:_(<2 x s32>) = G_SHL %src, %thirty3_splat1440 %copy2:_(<2 x s32>) = COPY %biggerSized1441)";1442 setUp(MIRString);1443 if (!TM)1444 GTEST_SKIP();1445 1446 Register EqSizedCopyReg = Copies[Copies.size() - 2];1447 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);1448 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();1449 1450 Register BiggerSizedCopyReg = Copies[Copies.size() - 1];1451 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);1452 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();1453 1454 GISelValueTracking Info(*MF);1455 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);1456 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);1457 1458 EXPECT_TRUE(EqSizeRes.One.isZero());1459 EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());1460 1461 EXPECT_TRUE(BiggerSizeRes.One.isZero());1462 EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());1463}1464 1465TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) {1466 StringRef MIRString = R"(1467 %copy_x0:_(s64) = COPY $x01468 %copy_x1:_(s64) = COPY $x11469 %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x11470 1471 %assert8:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 81472 %copy_assert8:_(<2 x s64>) = COPY %assert81473 1474 %assert1:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 11475 %copy_assert1:_(<2 x s64>) = COPY %assert11476 1477 %assert63:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 631478 %copy_assert63:_(<2 x s64>) = COPY %assert631479 1480 %assert3:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 31481 %copy_assert3:_(<2 x s64>) = COPY %assert31482)";1483 1484 setUp(MIRString);1485 if (!TM)1486 GTEST_SKIP();1487 1488 Register CopyAssert8 = Copies[Copies.size() - 4];1489 Register CopyAssert1 = Copies[Copies.size() - 3];1490 Register CopyAssert63 = Copies[Copies.size() - 2];1491 Register CopyAssert3 = Copies[Copies.size() - 1];1492 1493 GISelValueTracking Info(*MF);1494 MachineInstr *Copy;1495 Register SrcReg;1496 KnownBits Res;1497 1498 // Assert zero-extension from an 8-bit value.1499 Copy = MRI->getVRegDef(CopyAssert8);1500 SrcReg = Copy->getOperand(1).getReg();1501 Res = Info.getKnownBits(SrcReg);1502 EXPECT_EQ(64u, Res.getBitWidth());1503 EXPECT_EQ(0u, Res.One.getZExtValue());1504 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());1505 1506 // Assert zero-extension from a 1-bit value.1507 Copy = MRI->getVRegDef(CopyAssert1);1508 SrcReg = Copy->getOperand(1).getReg();1509 Res = Info.getKnownBits(SrcReg);1510 EXPECT_EQ(64u, Res.getBitWidth());1511 EXPECT_EQ(0u, Res.One.getZExtValue());1512 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());1513 1514 // Assert zero-extension from a 63-bit value.1515 Copy = MRI->getVRegDef(CopyAssert63);1516 SrcReg = Copy->getOperand(1).getReg();1517 Res = Info.getKnownBits(SrcReg);1518 EXPECT_EQ(64u, Res.getBitWidth());1519 EXPECT_EQ(0u, Res.One.getZExtValue());1520 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());1521 1522 // Assert zero-extension from a 3-bit value.1523 Copy = MRI->getVRegDef(CopyAssert3);1524 SrcReg = Copy->getOperand(1).getReg();1525 Res = Info.getKnownBits(SrcReg);1526 EXPECT_EQ(64u, Res.getBitWidth());1527 EXPECT_EQ(0u, Res.One.getZExtValue());1528 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());1529}1530 1531TEST_F(AArch64GISelMITest, TestNumSignBitsUAddoOverflow) {1532 StringRef MIRString = R"(1533 %copy_x0:_(s64) = COPY $x01534 %copy_x1:_(s64) = COPY $x11535 %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x11536 %uaddo:_(<2 x s64>), %overflow:_(<2 x s32>) = G_UADDO %x0_x1, %x0_x11537 %result:_(<2 x s32>) = COPY %overflow1538)";1539 1540 setUp(MIRString);1541 if (!TM)1542 GTEST_SKIP();1543 1544 Register CopyOverflow = Copies[Copies.size() - 1];1545 1546 GISelValueTracking Info(*MF);1547 1548 // Assert sign-extension from vector boolean1549 EXPECT_EQ(32u, Info.computeNumSignBits(CopyOverflow));1550}1551