84 lines · cpp
1//===- llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp ----------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "llvm/MC/MCRegisterInfo.h"10#include "llvm/MC/MCTargetOptions.h"11#include "llvm/MC/TargetRegistry.h"12#include "llvm/Support/TargetSelect.h"13#include "llvm/Target/TargetMachine.h"14#include "gtest/gtest.h"15#include <mutex>16#include <thread>17 18using namespace llvm;19 20std::once_flag flag;21 22void InitializeAMDGPUTarget() {23 std::call_once(flag, []() {24 LLVMInitializeAMDGPUTargetInfo();25 LLVMInitializeAMDGPUTarget();26 LLVMInitializeAMDGPUTargetMC();27 });28}29 30std::unique_ptr<TargetMachine>31createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {32 InitializeAMDGPUTarget();33 34 std::string Error;35 Triple TT(TStr);36 const Target *T = TargetRegistry::lookupTarget(TT, Error);37 if (!T)38 return nullptr;39 40 TargetOptions Options;41 return std::unique_ptr<TargetMachine>(42 T->createTargetMachine(TT, CPU, FS, Options, std::nullopt, std::nullopt));43}44 45TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {46 for (auto Triple :47 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {48 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");49 if (TM && TM->getMCRegisterInfo()) {50 auto MRI = TM->getMCRegisterInfo();51 // Wave64 Dwarf register mapping test numbers52 // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,53 // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,54 // A0 => 3072, A255 => 332755 for (int DwarfEncoding :56 {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {57 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);58 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));59 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));60 }61 }62 }63}64 65TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {66 for (auto Triple :67 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {68 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");69 if (TM && TM->getMCRegisterInfo()) {70 auto MRI = TM->getMCRegisterInfo();71 // Wave32 Dwarf register mapping test numbers72 // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,73 // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,74 // A0 => 2048, A255 => 230375 for (int DwarfEncoding :76 {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {77 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);78 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));79 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));80 }81 }82 }83}84