76 lines · cpp
1//===- llvm/unittests/Target/AMDGPU/CSETest.cpp ---------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "AMDGPUTargetMachine.h"10#include "AMDGPUUnitTests.h"11#include "llvm/CodeGen/GlobalISel/CSEInfo.h"12#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"13#include "llvm/CodeGen/MachineModuleInfo.h"14#include "gtest/gtest.h"15 16using namespace llvm;17 18TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) {19 auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", "");20 if (!TM)21 GTEST_SKIP();22 23 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),24 std::string(TM->getTargetFeatureString()), *TM);25 26 LLVMContext Ctx;27 Module Mod("Module", Ctx);28 Mod.setDataLayout(TM->createDataLayout());29 30 auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false);31 auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod);32 33 MachineModuleInfo MMI(TM.get());34 auto MF =35 std::make_unique<MachineFunction>(*F, *TM, ST, MMI.getContext(), 42);36 auto *BB = MF->CreateMachineBasicBlock();37 MF->push_back(BB);38 39 MachineIRBuilder B(*MF);40 B.setMBB(*BB);41 42 LLT S32{LLT::scalar(32)};43 Register R0 = B.buildCopy(S32, Register(AMDGPU::SGPR0)).getReg(0);44 Register R1 = B.buildCopy(S32, Register(AMDGPU::SGPR1)).getReg(0);45 46 GISelCSEInfo CSEInfo;47 CSEInfo.setCSEConfig(std::make_unique<CSEConfigFull>());48 CSEInfo.analyze(*MF);49 B.setCSEInfo(&CSEInfo);50 CSEMIRBuilder CSEB(B.getState());51 CSEB.setInsertPt(B.getMBB(), B.getInsertPt());52 53 const RegisterBankInfo &RBI = *MF->getSubtarget().getRegBankInfo();54 55 const TargetRegisterClass *SgprRC = &AMDGPU::SReg_32RegClass;56 const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);57 MachineRegisterInfo::VRegAttrs SgprRCS32 = {SgprRC, S32};58 MachineRegisterInfo::VRegAttrs SgprRBS32 = {SgprRB, S32};59 60 auto Add = CSEB.buildAdd(S32, R0, R1);61 auto AddRC = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRCS32}, {R0, R1});62 auto AddRB = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRB, S32}}, {R0, R1});63 64 EXPECT_NE(Add, AddRC);65 EXPECT_NE(Add, AddRB);66 EXPECT_NE(AddRC, AddRB);67 68 auto Add_CSE = CSEB.buildAdd(S32, R0, R1);69 auto AddRC_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRC, S32}}, {R0, R1});70 auto AddRB_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRBS32}, {R0, R1});71 72 EXPECT_EQ(Add, Add_CSE);73 EXPECT_EQ(AddRC, AddRC_CSE);74 EXPECT_EQ(AddRB, AddRB_CSE);75}76