100 lines · cpp
1//===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "AMDGPUTargetMachine.h"10#include "AMDGPUUnitTests.h"11#include "gtest/gtest.h"12 13using namespace llvm;14 15TEST(AMDGPU, TestWave64DwarfRegMapping) {16 for (auto Triple :17 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {18 auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64");19 if (TM) {20 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),21 std::string(TM->getTargetFeatureString()), *TM);22 auto MRI = ST.getRegisterInfo();23 if (MRI) {24 // Wave64 Dwarf register mapping test numbers25 // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,26 // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,27 // A0 => 3072, A255 => 332728 for (int DwarfEncoding :29 {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {30 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);31 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));32 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));33 }34 35 // We should get the correct LLVM register when round tripping through36 // the dwarf encoding.37 for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {38 int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);39 EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));40 }41 42 // Verify that subregisters have no dwarf encoding.43 for (MCRegister LLSubReg :44 {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {45 EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);46 }47 48 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR511, false), 3071);49 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR512, false), -1);50 }51 }52 }53}54 55TEST(AMDGPU, TestWave32DwarfRegMapping) {56 for (auto Triple :57 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {58 auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32");59 if (TM) {60 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),61 std::string(TM->getTargetFeatureString()), *TM);62 auto MRI = ST.getRegisterInfo();63 if (MRI) {64 // Wave32 Dwarf register mapping test numbers65 // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,66 // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,67 // A0 => 2048, A255 => 230368 for (int DwarfEncoding :69 {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {70 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);71 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));72 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));73 }74 75 // We should get the correct LLVM register when round tripping through76 // the dwarf encoding.77 for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {78 int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);79 EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));80 }81 82 // Verify that subregisters have no dwarf encoding.83 for (MCRegister LLSubReg :84 {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {85 EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);86 }87 88 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR511, false), 2047);89 EXPECT_EQ(MRI->getLLVMRegNum(2047, false), AMDGPU::VGPR511);90 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR512, false), 3584);91 EXPECT_EQ(MRI->getLLVMRegNum(3584, false), AMDGPU::VGPR512);92 93 // Verify that subregisters have no dwarf encoding.94 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR511_LO16, false), -1);95 EXPECT_EQ(MRI->getDwarfRegNum(AMDGPU::VGPR512_LO16, false), -1);96 }97 }98 }99}100