2088 lines · cpp
1#include "ARMBaseInstrInfo.h"2#include "ARMSubtarget.h"3#include "ARMTargetMachine.h"4#include "llvm/MC/TargetRegistry.h"5#include "llvm/Support/TargetSelect.h"6#include "llvm/Target/TargetMachine.h"7#include "llvm/Target/TargetOptions.h"8 9#include "gtest/gtest.h"10 11using namespace llvm;12 13TEST(MachineInstructionDoubleWidthResult, IsCorrect) {14 using namespace ARM;15 16 auto DoubleWidthResult = [](unsigned Opcode) {17 switch (Opcode) {18 default:19 break;20 case MVE_VMULLBp16:21 case MVE_VMULLBp8:22 case MVE_VMULLBs16:23 case MVE_VMULLBs32:24 case MVE_VMULLBs8:25 case MVE_VMULLBu16:26 case MVE_VMULLBu32:27 case MVE_VMULLBu8:28 case MVE_VMULLTp16:29 case MVE_VMULLTp8:30 case MVE_VMULLTs16:31 case MVE_VMULLTs32:32 case MVE_VMULLTs8:33 case MVE_VMULLTu16:34 case MVE_VMULLTu32:35 case MVE_VMULLTu8:36 case MVE_VQDMULL_qr_s16bh:37 case MVE_VQDMULL_qr_s16th:38 case MVE_VQDMULL_qr_s32bh:39 case MVE_VQDMULL_qr_s32th:40 case MVE_VQDMULLs16bh:41 case MVE_VQDMULLs16th:42 case MVE_VQDMULLs32bh:43 case MVE_VQDMULLs32th:44 case MVE_VMOVLs16bh:45 case MVE_VMOVLs16th:46 case MVE_VMOVLs8bh:47 case MVE_VMOVLs8th:48 case MVE_VMOVLu16bh:49 case MVE_VMOVLu16th:50 case MVE_VMOVLu8bh:51 case MVE_VMOVLu8th:52 case MVE_VSHLL_imms16bh:53 case MVE_VSHLL_imms16th:54 case MVE_VSHLL_imms8bh:55 case MVE_VSHLL_imms8th:56 case MVE_VSHLL_immu16bh:57 case MVE_VSHLL_immu16th:58 case MVE_VSHLL_immu8bh:59 case MVE_VSHLL_immu8th:60 case MVE_VSHLL_lws16bh:61 case MVE_VSHLL_lws16th:62 case MVE_VSHLL_lws8bh:63 case MVE_VSHLL_lws8th:64 case MVE_VSHLL_lwu16bh:65 case MVE_VSHLL_lwu16th:66 case MVE_VSHLL_lwu8bh:67 case MVE_VSHLL_lwu8th:68 return true;69 }70 return false;71 };72 73 LLVMInitializeARMTargetInfo();74 LLVMInitializeARMTarget();75 LLVMInitializeARMTargetMC();76 77 Triple TT("thumbv8.1m.main-none-none-eabi");78 std::string Error;79 const Target *T = TargetRegistry::lookupTarget(TT, Error);80 if (!T) {81 dbgs() << Error;82 GTEST_SKIP();83 }84 85 TargetOptions Options;86 auto TM = std::unique_ptr<TargetMachine>(87 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,88 std::nullopt, CodeGenOptLevel::Default));89 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),90 std::string(TM->getTargetFeatureString()),91 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);92 const ARMBaseInstrInfo *TII = ST.getInstrInfo();93 auto MII = TM->getMCInstrInfo();94 95 for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {96 const MCInstrDesc &Desc = TII->get(i);97 98 uint64_t Flags = Desc.TSFlags;99 if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)100 continue;101 102 bool Valid = (Flags & ARMII::DoubleWidthResult) != 0;103 ASSERT_EQ(DoubleWidthResult(i), Valid)104 << MII->getName(i)105 << ": mismatched expectation for tail-predicated safety\n";106 }107}108 109TEST(MachineInstructionHorizontalReduction, IsCorrect) {110 using namespace ARM;111 112 auto HorizontalReduction = [](unsigned Opcode) {113 switch (Opcode) {114 default:115 break;116 case MVE_VABAVs16:117 case MVE_VABAVs32:118 case MVE_VABAVs8:119 case MVE_VABAVu16:120 case MVE_VABAVu32:121 case MVE_VABAVu8:122 case MVE_VADDLVs32acc:123 case MVE_VADDLVs32no_acc:124 case MVE_VADDLVu32acc:125 case MVE_VADDLVu32no_acc:126 case MVE_VADDVs16acc:127 case MVE_VADDVs16no_acc:128 case MVE_VADDVs32acc:129 case MVE_VADDVs32no_acc:130 case MVE_VADDVs8acc:131 case MVE_VADDVs8no_acc:132 case MVE_VADDVu16acc:133 case MVE_VADDVu16no_acc:134 case MVE_VADDVu32acc:135 case MVE_VADDVu32no_acc:136 case MVE_VADDVu8acc:137 case MVE_VADDVu8no_acc:138 case MVE_VMAXAVs16:139 case MVE_VMAXAVs32:140 case MVE_VMAXAVs8:141 case MVE_VMAXNMAVf16:142 case MVE_VMAXNMAVf32:143 case MVE_VMAXNMVf16:144 case MVE_VMAXNMVf32:145 case MVE_VMAXVs16:146 case MVE_VMAXVs32:147 case MVE_VMAXVs8:148 case MVE_VMAXVu16:149 case MVE_VMAXVu32:150 case MVE_VMAXVu8:151 case MVE_VMINAVs16:152 case MVE_VMINAVs32:153 case MVE_VMINAVs8:154 case MVE_VMINNMAVf16:155 case MVE_VMINNMAVf32:156 case MVE_VMINNMVf16:157 case MVE_VMINNMVf32:158 case MVE_VMINVs16:159 case MVE_VMINVs32:160 case MVE_VMINVs8:161 case MVE_VMINVu16:162 case MVE_VMINVu32:163 case MVE_VMINVu8:164 case MVE_VMLADAVas16:165 case MVE_VMLADAVas32:166 case MVE_VMLADAVas8:167 case MVE_VMLADAVau16:168 case MVE_VMLADAVau32:169 case MVE_VMLADAVau8:170 case MVE_VMLADAVaxs16:171 case MVE_VMLADAVaxs32:172 case MVE_VMLADAVaxs8:173 case MVE_VMLADAVs16:174 case MVE_VMLADAVs32:175 case MVE_VMLADAVs8:176 case MVE_VMLADAVu16:177 case MVE_VMLADAVu32:178 case MVE_VMLADAVu8:179 case MVE_VMLADAVxs16:180 case MVE_VMLADAVxs32:181 case MVE_VMLADAVxs8:182 case MVE_VMLALDAVas16:183 case MVE_VMLALDAVas32:184 case MVE_VMLALDAVau16:185 case MVE_VMLALDAVau32:186 case MVE_VMLALDAVaxs16:187 case MVE_VMLALDAVaxs32:188 case MVE_VMLALDAVs16:189 case MVE_VMLALDAVs32:190 case MVE_VMLALDAVu16:191 case MVE_VMLALDAVu32:192 case MVE_VMLALDAVxs16:193 case MVE_VMLALDAVxs32:194 case MVE_VMLSDAVas16:195 case MVE_VMLSDAVas32:196 case MVE_VMLSDAVas8:197 case MVE_VMLSDAVaxs16:198 case MVE_VMLSDAVaxs32:199 case MVE_VMLSDAVaxs8:200 case MVE_VMLSDAVs16:201 case MVE_VMLSDAVs32:202 case MVE_VMLSDAVs8:203 case MVE_VMLSDAVxs16:204 case MVE_VMLSDAVxs32:205 case MVE_VMLSDAVxs8:206 case MVE_VMLSLDAVas16:207 case MVE_VMLSLDAVas32:208 case MVE_VMLSLDAVaxs16:209 case MVE_VMLSLDAVaxs32:210 case MVE_VMLSLDAVs16:211 case MVE_VMLSLDAVs32:212 case MVE_VMLSLDAVxs16:213 case MVE_VMLSLDAVxs32:214 case MVE_VRMLALDAVHas32:215 case MVE_VRMLALDAVHau32:216 case MVE_VRMLALDAVHaxs32:217 case MVE_VRMLALDAVHs32:218 case MVE_VRMLALDAVHu32:219 case MVE_VRMLALDAVHxs32:220 case MVE_VRMLSLDAVHas32:221 case MVE_VRMLSLDAVHaxs32:222 case MVE_VRMLSLDAVHs32:223 case MVE_VRMLSLDAVHxs32:224 return true;225 }226 return false;227 };228 229 LLVMInitializeARMTargetInfo();230 LLVMInitializeARMTarget();231 LLVMInitializeARMTargetMC();232 233 Triple TT("thumbv8.1m.main-none-none-eabi");234 std::string Error;235 const Target *T = TargetRegistry::lookupTarget(TT, Error);236 if (!T) {237 dbgs() << Error;238 GTEST_SKIP();239 }240 241 TargetOptions Options;242 auto TM = std::unique_ptr<TargetMachine>(243 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,244 std::nullopt, CodeGenOptLevel::Default));245 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),246 std::string(TM->getTargetFeatureString()),247 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);248 const ARMBaseInstrInfo *TII = ST.getInstrInfo();249 auto MII = TM->getMCInstrInfo();250 251 for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {252 const MCInstrDesc &Desc = TII->get(i);253 254 uint64_t Flags = Desc.TSFlags;255 if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)256 continue;257 bool Valid = (Flags & ARMII::HorizontalReduction) != 0;258 ASSERT_EQ(HorizontalReduction(i), Valid)259 << MII->getName(i)260 << ": mismatched expectation for tail-predicated safety\n";261 }262}263 264TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {265 using namespace ARM;266 267 auto RetainsPreviousHalfElement = [](unsigned Opcode) {268 switch (Opcode) {269 default:270 break;271 case MVE_VMOVNi16bh:272 case MVE_VMOVNi16th:273 case MVE_VMOVNi32bh:274 case MVE_VMOVNi32th:275 case MVE_VQMOVNs16bh:276 case MVE_VQMOVNs16th:277 case MVE_VQMOVNs32bh:278 case MVE_VQMOVNs32th:279 case MVE_VQMOVNu16bh:280 case MVE_VQMOVNu16th:281 case MVE_VQMOVNu32bh:282 case MVE_VQMOVNu32th:283 case MVE_VQMOVUNs16bh:284 case MVE_VQMOVUNs16th:285 case MVE_VQMOVUNs32bh:286 case MVE_VQMOVUNs32th:287 case MVE_VQRSHRNbhs16:288 case MVE_VQRSHRNbhs32:289 case MVE_VQRSHRNbhu16:290 case MVE_VQRSHRNbhu32:291 case MVE_VQRSHRNths16:292 case MVE_VQRSHRNths32:293 case MVE_VQRSHRNthu16:294 case MVE_VQRSHRNthu32:295 case MVE_VQRSHRUNs16bh:296 case MVE_VQRSHRUNs16th:297 case MVE_VQRSHRUNs32bh:298 case MVE_VQRSHRUNs32th:299 case MVE_VQSHRNbhs16:300 case MVE_VQSHRNbhs32:301 case MVE_VQSHRNbhu16:302 case MVE_VQSHRNbhu32:303 case MVE_VQSHRNths16:304 case MVE_VQSHRNths32:305 case MVE_VQSHRNthu16:306 case MVE_VQSHRNthu32:307 case MVE_VQSHRUNs16bh:308 case MVE_VQSHRUNs16th:309 case MVE_VQSHRUNs32bh:310 case MVE_VQSHRUNs32th:311 case MVE_VRSHRNi16bh:312 case MVE_VRSHRNi16th:313 case MVE_VRSHRNi32bh:314 case MVE_VRSHRNi32th:315 case MVE_VSHRNi16bh:316 case MVE_VSHRNi16th:317 case MVE_VSHRNi32bh:318 case MVE_VSHRNi32th:319 case MVE_VCVTf16f32bh:320 case MVE_VCVTf16f32th:321 case MVE_VCVTf32f16bh:322 case MVE_VCVTf32f16th:323 return true;324 }325 return false;326 };327 328 LLVMInitializeARMTargetInfo();329 LLVMInitializeARMTarget();330 LLVMInitializeARMTargetMC();331 332 Triple TT("thumbv8.1m.main-none-none-eabi");333 std::string Error;334 const Target *T = TargetRegistry::lookupTarget(TT, Error);335 if (!T) {336 dbgs() << Error;337 GTEST_SKIP();338 }339 340 TargetOptions Options;341 auto TM = std::unique_ptr<TargetMachine>(342 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,343 std::nullopt, CodeGenOptLevel::Default));344 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),345 std::string(TM->getTargetFeatureString()),346 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);347 const ARMBaseInstrInfo *TII = ST.getInstrInfo();348 auto MII = TM->getMCInstrInfo();349 350 for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {351 const MCInstrDesc &Desc = TII->get(i);352 353 uint64_t Flags = Desc.TSFlags;354 if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)355 continue;356 357 bool Valid = (Flags & ARMII::RetainsPreviousHalfElement) != 0;358 ASSERT_EQ(RetainsPreviousHalfElement(i), Valid)359 << MII->getName(i)360 << ": mismatched expectation for tail-predicated safety\n";361 }362}363// Test for instructions that aren't immediately obviously valid within a364// tail-predicated loop. This should be marked up in their tablegen365// descriptions. Currently we, conservatively, disallow:366// - cross beat carries.367// - complex operations.368// - horizontal operations with exchange.369// - byte swapping.370// - interleaved memory instructions.371// TODO: Add to this list once we can handle them safely.372TEST(MachineInstrValidTailPredication, IsCorrect) {373 374 using namespace ARM;375 376 auto IsValidTPOpcode = [](unsigned Opcode) {377 switch (Opcode) {378 default:379 return false;380 case MVE_ASRLi:381 case MVE_ASRLr:382 case MVE_LSRL:383 case MVE_LSLLi:384 case MVE_LSLLr:385 case MVE_SQRSHR:386 case MVE_SQRSHRL:387 case MVE_SQSHL:388 case MVE_SQSHLL:389 case MVE_SRSHR:390 case MVE_SRSHRL:391 case MVE_UQRSHL:392 case MVE_UQRSHLL:393 case MVE_UQSHL:394 case MVE_UQSHLL:395 case MVE_URSHR:396 case MVE_URSHRL:397 case MVE_VABDf16:398 case MVE_VABDf32:399 case MVE_VABDs16:400 case MVE_VABDs32:401 case MVE_VABDs8:402 case MVE_VABDu16:403 case MVE_VABDu32:404 case MVE_VABDu8:405 case MVE_VABSf16:406 case MVE_VABSf32:407 case MVE_VABSs16:408 case MVE_VABSs32:409 case MVE_VABSs8:410 case MVE_VADD_qr_f16:411 case MVE_VADD_qr_f32:412 case MVE_VADD_qr_i16:413 case MVE_VADD_qr_i32:414 case MVE_VADD_qr_i8:415 case MVE_VADDVs16acc:416 case MVE_VADDVs16no_acc:417 case MVE_VADDVs32acc:418 case MVE_VADDVs32no_acc:419 case MVE_VADDVs8acc:420 case MVE_VADDVs8no_acc:421 case MVE_VADDVu16acc:422 case MVE_VADDVu16no_acc:423 case MVE_VADDVu32acc:424 case MVE_VADDVu32no_acc:425 case MVE_VADDVu8acc:426 case MVE_VADDVu8no_acc:427 case MVE_VADDf16:428 case MVE_VADDf32:429 case MVE_VADDi16:430 case MVE_VADDi32:431 case MVE_VADDi8:432 case MVE_VAND:433 case MVE_VBIC:434 case MVE_VBICimmi16:435 case MVE_VBICimmi32:436 case MVE_VBRSR16:437 case MVE_VBRSR32:438 case MVE_VBRSR8:439 case MVE_VCLSs16:440 case MVE_VCLSs32:441 case MVE_VCLSs8:442 case MVE_VCLZs16:443 case MVE_VCLZs32:444 case MVE_VCLZs8:445 case MVE_VCMPf16:446 case MVE_VCMPf16r:447 case MVE_VCMPf32:448 case MVE_VCMPf32r:449 case MVE_VCMPi16:450 case MVE_VCMPi16r:451 case MVE_VCMPi32:452 case MVE_VCMPi32r:453 case MVE_VCMPi8:454 case MVE_VCMPi8r:455 case MVE_VCMPs16:456 case MVE_VCMPs16r:457 case MVE_VCMPs32:458 case MVE_VCMPs32r:459 case MVE_VCMPs8:460 case MVE_VCMPs8r:461 case MVE_VCMPu16:462 case MVE_VCMPu16r:463 case MVE_VCMPu32:464 case MVE_VCMPu32r:465 case MVE_VCMPu8:466 case MVE_VCMPu8r:467 case MVE_VCTP16:468 case MVE_VCTP32:469 case MVE_VCTP64:470 case MVE_VCTP8:471 case MVE_VCVTf16s16_fix:472 case MVE_VCVTf16s16n:473 case MVE_VCVTf16u16_fix:474 case MVE_VCVTf16u16n:475 case MVE_VCVTf32s32_fix:476 case MVE_VCVTf32s32n:477 case MVE_VCVTf32u32_fix:478 case MVE_VCVTf32u32n:479 case MVE_VCVTs16f16_fix:480 case MVE_VCVTs16f16a:481 case MVE_VCVTs16f16m:482 case MVE_VCVTs16f16n:483 case MVE_VCVTs16f16p:484 case MVE_VCVTs16f16z:485 case MVE_VCVTs32f32_fix:486 case MVE_VCVTs32f32a:487 case MVE_VCVTs32f32m:488 case MVE_VCVTs32f32n:489 case MVE_VCVTs32f32p:490 case MVE_VCVTs32f32z:491 case MVE_VCVTu16f16_fix:492 case MVE_VCVTu16f16a:493 case MVE_VCVTu16f16m:494 case MVE_VCVTu16f16n:495 case MVE_VCVTu16f16p:496 case MVE_VCVTu16f16z:497 case MVE_VCVTu32f32_fix:498 case MVE_VCVTu32f32a:499 case MVE_VCVTu32f32m:500 case MVE_VCVTu32f32n:501 case MVE_VCVTu32f32p:502 case MVE_VCVTu32f32z:503 case MVE_VDDUPu16:504 case MVE_VDDUPu32:505 case MVE_VDDUPu8:506 case MVE_VDUP16:507 case MVE_VDUP32:508 case MVE_VDUP8:509 case MVE_VDWDUPu16:510 case MVE_VDWDUPu32:511 case MVE_VDWDUPu8:512 case MVE_VEOR:513 case MVE_VFMA_qr_Sf16:514 case MVE_VFMA_qr_Sf32:515 case MVE_VFMA_qr_f16:516 case MVE_VFMA_qr_f32:517 case MVE_VFMAf16:518 case MVE_VFMAf32:519 case MVE_VFMSf16:520 case MVE_VFMSf32:521 case MVE_VMAXAs16:522 case MVE_VMAXAs32:523 case MVE_VMAXAs8:524 case MVE_VMAXs16:525 case MVE_VMAXs32:526 case MVE_VMAXs8:527 case MVE_VMAXu16:528 case MVE_VMAXu32:529 case MVE_VMAXu8:530 case MVE_VMAXNMf16:531 case MVE_VMAXNMf32:532 case MVE_VMAXNMAf16:533 case MVE_VMAXNMAf32:534 case MVE_VMINAs16:535 case MVE_VMINAs32:536 case MVE_VMINAs8:537 case MVE_VMINs16:538 case MVE_VMINs32:539 case MVE_VMINs8:540 case MVE_VMINu16:541 case MVE_VMINu32:542 case MVE_VMINu8:543 case MVE_VMINNMf16:544 case MVE_VMINNMf32:545 case MVE_VMINNMAf16:546 case MVE_VMINNMAf32:547 case MVE_VMLADAVas16:548 case MVE_VMLADAVas32:549 case MVE_VMLADAVas8:550 case MVE_VMLADAVau16:551 case MVE_VMLADAVau32:552 case MVE_VMLADAVau8:553 case MVE_VMLADAVs16:554 case MVE_VMLADAVs32:555 case MVE_VMLADAVs8:556 case MVE_VMLADAVu16:557 case MVE_VMLADAVu32:558 case MVE_VMLADAVu8:559 case MVE_VMLALDAVs16:560 case MVE_VMLALDAVs32:561 case MVE_VMLALDAVu16:562 case MVE_VMLALDAVu32:563 case MVE_VMLALDAVas16:564 case MVE_VMLALDAVas32:565 case MVE_VMLALDAVau16:566 case MVE_VMLALDAVau32:567 case MVE_VMLSDAVas16:568 case MVE_VMLSDAVas32:569 case MVE_VMLSDAVas8:570 case MVE_VMLSDAVs16:571 case MVE_VMLSDAVs32:572 case MVE_VMLSDAVs8:573 case MVE_VMLSLDAVas16:574 case MVE_VMLSLDAVas32:575 case MVE_VMLSLDAVs16:576 case MVE_VMLSLDAVs32:577 case MVE_VRMLALDAVHas32:578 case MVE_VRMLALDAVHau32:579 case MVE_VRMLALDAVHs32:580 case MVE_VRMLALDAVHu32:581 case MVE_VRMLSLDAVHas32:582 case MVE_VRMLSLDAVHs32:583 case MVE_VMLAS_qr_i16:584 case MVE_VMLAS_qr_i32:585 case MVE_VMLAS_qr_i8:586 case MVE_VMLA_qr_i16:587 case MVE_VMLA_qr_i32:588 case MVE_VMLA_qr_i8:589 case MVE_VHADD_qr_s16:590 case MVE_VHADD_qr_s32:591 case MVE_VHADD_qr_s8:592 case MVE_VHADD_qr_u16:593 case MVE_VHADD_qr_u32:594 case MVE_VHADD_qr_u8:595 case MVE_VHADDs16:596 case MVE_VHADDs32:597 case MVE_VHADDs8:598 case MVE_VHADDu16:599 case MVE_VHADDu32:600 case MVE_VHADDu8:601 case MVE_VHSUB_qr_s16:602 case MVE_VHSUB_qr_s32:603 case MVE_VHSUB_qr_s8:604 case MVE_VHSUB_qr_u16:605 case MVE_VHSUB_qr_u32:606 case MVE_VHSUB_qr_u8:607 case MVE_VHSUBs16:608 case MVE_VHSUBs32:609 case MVE_VHSUBs8:610 case MVE_VHSUBu16:611 case MVE_VHSUBu32:612 case MVE_VHSUBu8:613 case MVE_VIDUPu16:614 case MVE_VIDUPu32:615 case MVE_VIDUPu8:616 case MVE_VIWDUPu16:617 case MVE_VIWDUPu32:618 case MVE_VIWDUPu8:619 case MVE_VLD20_8:620 case MVE_VLD21_8:621 case MVE_VLD20_16:622 case MVE_VLD21_16:623 case MVE_VLD20_32:624 case MVE_VLD21_32:625 case MVE_VLD20_8_wb:626 case MVE_VLD21_8_wb:627 case MVE_VLD20_16_wb:628 case MVE_VLD21_16_wb:629 case MVE_VLD20_32_wb:630 case MVE_VLD21_32_wb:631 case MVE_VLD40_8:632 case MVE_VLD41_8:633 case MVE_VLD42_8:634 case MVE_VLD43_8:635 case MVE_VLD40_16:636 case MVE_VLD41_16:637 case MVE_VLD42_16:638 case MVE_VLD43_16:639 case MVE_VLD40_32:640 case MVE_VLD41_32:641 case MVE_VLD42_32:642 case MVE_VLD43_32:643 case MVE_VLD40_8_wb:644 case MVE_VLD41_8_wb:645 case MVE_VLD42_8_wb:646 case MVE_VLD43_8_wb:647 case MVE_VLD40_16_wb:648 case MVE_VLD41_16_wb:649 case MVE_VLD42_16_wb:650 case MVE_VLD43_16_wb:651 case MVE_VLD40_32_wb:652 case MVE_VLD41_32_wb:653 case MVE_VLD42_32_wb:654 case MVE_VLD43_32_wb:655 case MVE_VLDRBS16:656 case MVE_VLDRBS16_post:657 case MVE_VLDRBS16_pre:658 case MVE_VLDRBS16_rq:659 case MVE_VLDRBS32:660 case MVE_VLDRBS32_post:661 case MVE_VLDRBS32_pre:662 case MVE_VLDRBS32_rq:663 case MVE_VLDRBU16:664 case MVE_VLDRBU16_post:665 case MVE_VLDRBU16_pre:666 case MVE_VLDRBU16_rq:667 case MVE_VLDRBU32:668 case MVE_VLDRBU32_post:669 case MVE_VLDRBU32_pre:670 case MVE_VLDRBU32_rq:671 case MVE_VLDRBU8:672 case MVE_VLDRBU8_post:673 case MVE_VLDRBU8_pre:674 case MVE_VLDRBU8_rq:675 case MVE_VLDRDU64_qi:676 case MVE_VLDRDU64_qi_pre:677 case MVE_VLDRDU64_rq:678 case MVE_VLDRDU64_rq_u:679 case MVE_VLDRHS32:680 case MVE_VLDRHS32_post:681 case MVE_VLDRHS32_pre:682 case MVE_VLDRHS32_rq:683 case MVE_VLDRHS32_rq_u:684 case MVE_VLDRHU16:685 case MVE_VLDRHU16_post:686 case MVE_VLDRHU16_pre:687 case MVE_VLDRHU16_rq:688 case MVE_VLDRHU16_rq_u:689 case MVE_VLDRHU32:690 case MVE_VLDRHU32_post:691 case MVE_VLDRHU32_pre:692 case MVE_VLDRHU32_rq:693 case MVE_VLDRHU32_rq_u:694 case MVE_VLDRWU32:695 case MVE_VLDRWU32_post:696 case MVE_VLDRWU32_pre:697 case MVE_VLDRWU32_qi:698 case MVE_VLDRWU32_qi_pre:699 case MVE_VLDRWU32_rq:700 case MVE_VLDRWU32_rq_u:701 case MVE_VMOVimmf32:702 case MVE_VMOVimmi16:703 case MVE_VMOVimmi32:704 case MVE_VMOVimmi64:705 case MVE_VMOVimmi8:706 case MVE_VMOVNi16bh:707 case MVE_VMOVNi16th:708 case MVE_VMOVNi32bh:709 case MVE_VMOVNi32th:710 case MVE_VMULLBp16:711 case MVE_VMULLBp8:712 case MVE_VMULLBs16:713 case MVE_VMULLBs32:714 case MVE_VMULLBs8:715 case MVE_VMULLBu16:716 case MVE_VMULLBu32:717 case MVE_VMULLBu8:718 case MVE_VMULLTp16:719 case MVE_VMULLTp8:720 case MVE_VMULLTs16:721 case MVE_VMULLTs32:722 case MVE_VMULLTs8:723 case MVE_VMULLTu16:724 case MVE_VMULLTu32:725 case MVE_VMULLTu8:726 case MVE_VMUL_qr_f16:727 case MVE_VMUL_qr_f32:728 case MVE_VMUL_qr_i16:729 case MVE_VMUL_qr_i32:730 case MVE_VMUL_qr_i8:731 case MVE_VMULf16:732 case MVE_VMULf32:733 case MVE_VMULi16:734 case MVE_VMULi8:735 case MVE_VMULi32:736 case MVE_VMULHs32:737 case MVE_VMULHs16:738 case MVE_VMULHs8:739 case MVE_VMULHu32:740 case MVE_VMULHu16:741 case MVE_VMULHu8:742 case MVE_VMVN:743 case MVE_VMVNimmi16:744 case MVE_VMVNimmi32:745 case MVE_VNEGf16:746 case MVE_VNEGf32:747 case MVE_VNEGs16:748 case MVE_VNEGs32:749 case MVE_VNEGs8:750 case MVE_VORN:751 case MVE_VORR:752 case MVE_VORRimmi16:753 case MVE_VORRimmi32:754 case MVE_VPST:755 case MVE_VPTv16i8:756 case MVE_VPTv8i16:757 case MVE_VPTv4i32:758 case MVE_VPTv16i8r:759 case MVE_VPTv8i16r:760 case MVE_VPTv4i32r:761 case MVE_VPTv16s8:762 case MVE_VPTv8s16:763 case MVE_VPTv4s32:764 case MVE_VPTv16s8r:765 case MVE_VPTv8s16r:766 case MVE_VPTv4s32r:767 case MVE_VPTv16u8:768 case MVE_VPTv8u16:769 case MVE_VPTv4u32:770 case MVE_VPTv16u8r:771 case MVE_VPTv8u16r:772 case MVE_VPTv4u32r:773 case MVE_VPTv8f16:774 case MVE_VPTv4f32:775 case MVE_VPTv8f16r:776 case MVE_VPTv4f32r:777 case MVE_VQABSs16:778 case MVE_VQABSs32:779 case MVE_VQABSs8:780 case MVE_VQADD_qr_s16:781 case MVE_VQADD_qr_s32:782 case MVE_VQADD_qr_s8:783 case MVE_VQADD_qr_u16:784 case MVE_VQADD_qr_u32:785 case MVE_VQADD_qr_u8:786 case MVE_VQADDs16:787 case MVE_VQADDs32:788 case MVE_VQADDs8:789 case MVE_VQADDu16:790 case MVE_VQADDu32:791 case MVE_VQADDu8:792 case MVE_VQDMULH_qr_s16:793 case MVE_VQDMULH_qr_s32:794 case MVE_VQDMULH_qr_s8:795 case MVE_VQDMULHi16:796 case MVE_VQDMULHi32:797 case MVE_VQDMULHi8:798 case MVE_VQDMULL_qr_s16bh:799 case MVE_VQDMULL_qr_s16th:800 case MVE_VQDMULL_qr_s32bh:801 case MVE_VQDMULL_qr_s32th:802 case MVE_VQDMULLs16bh:803 case MVE_VQDMULLs16th:804 case MVE_VQDMULLs32bh:805 case MVE_VQDMULLs32th:806 case MVE_VQRDMULH_qr_s16:807 case MVE_VQRDMULH_qr_s32:808 case MVE_VQRDMULH_qr_s8:809 case MVE_VQRDMULHi16:810 case MVE_VQRDMULHi32:811 case MVE_VQRDMULHi8:812 case MVE_VQNEGs16:813 case MVE_VQNEGs32:814 case MVE_VQNEGs8:815 case MVE_VQMOVNs16bh:816 case MVE_VQMOVNs16th:817 case MVE_VQMOVNs32bh:818 case MVE_VQMOVNs32th:819 case MVE_VQMOVNu16bh:820 case MVE_VQMOVNu16th:821 case MVE_VQMOVNu32bh:822 case MVE_VQMOVNu32th:823 case MVE_VQMOVUNs16bh:824 case MVE_VQMOVUNs16th:825 case MVE_VQMOVUNs32bh:826 case MVE_VQMOVUNs32th:827 case MVE_VQRSHL_by_vecs16:828 case MVE_VQRSHL_by_vecs32:829 case MVE_VQRSHL_by_vecs8:830 case MVE_VQRSHL_by_vecu16:831 case MVE_VQRSHL_by_vecu32:832 case MVE_VQRSHL_by_vecu8:833 case MVE_VQRSHL_qrs16:834 case MVE_VQRSHL_qrs32:835 case MVE_VQRSHL_qrs8:836 case MVE_VQRSHL_qru16:837 case MVE_VQRSHL_qru8:838 case MVE_VQRSHL_qru32:839 case MVE_VQSHLU_imms16:840 case MVE_VQSHLU_imms32:841 case MVE_VQSHLU_imms8:842 case MVE_VQSHLimms16:843 case MVE_VQSHLimms32:844 case MVE_VQSHLimms8:845 case MVE_VQSHLimmu16:846 case MVE_VQSHLimmu32:847 case MVE_VQSHLimmu8:848 case MVE_VQSHL_by_vecs16:849 case MVE_VQSHL_by_vecs32:850 case MVE_VQSHL_by_vecs8:851 case MVE_VQSHL_by_vecu16:852 case MVE_VQSHL_by_vecu32:853 case MVE_VQSHL_by_vecu8:854 case MVE_VQSHL_qrs16:855 case MVE_VQSHL_qrs32:856 case MVE_VQSHL_qrs8:857 case MVE_VQSHL_qru16:858 case MVE_VQSHL_qru32:859 case MVE_VQSHL_qru8:860 case MVE_VQRSHRNbhs16:861 case MVE_VQRSHRNbhs32:862 case MVE_VQRSHRNbhu16:863 case MVE_VQRSHRNbhu32:864 case MVE_VQRSHRNths16:865 case MVE_VQRSHRNths32:866 case MVE_VQRSHRNthu16:867 case MVE_VQRSHRNthu32:868 case MVE_VQRSHRUNs16bh:869 case MVE_VQRSHRUNs16th:870 case MVE_VQRSHRUNs32bh:871 case MVE_VQRSHRUNs32th:872 case MVE_VQSHRNbhs16:873 case MVE_VQSHRNbhs32:874 case MVE_VQSHRNbhu16:875 case MVE_VQSHRNbhu32:876 case MVE_VQSHRNths16:877 case MVE_VQSHRNths32:878 case MVE_VQSHRNthu16:879 case MVE_VQSHRNthu32:880 case MVE_VQSHRUNs16bh:881 case MVE_VQSHRUNs16th:882 case MVE_VQSHRUNs32bh:883 case MVE_VQSHRUNs32th:884 case MVE_VQSUB_qr_s16:885 case MVE_VQSUB_qr_s32:886 case MVE_VQSUB_qr_s8:887 case MVE_VQSUB_qr_u16:888 case MVE_VQSUB_qr_u32:889 case MVE_VQSUB_qr_u8:890 case MVE_VQSUBs16:891 case MVE_VQSUBs32:892 case MVE_VQSUBs8:893 case MVE_VQSUBu16:894 case MVE_VQSUBu32:895 case MVE_VQSUBu8:896 case MVE_VRHADDs16:897 case MVE_VRHADDs32:898 case MVE_VRHADDs8:899 case MVE_VRHADDu16:900 case MVE_VRHADDu32:901 case MVE_VRHADDu8:902 case MVE_VRINTf16A:903 case MVE_VRINTf16M:904 case MVE_VRINTf16N:905 case MVE_VRINTf16P:906 case MVE_VRINTf16X:907 case MVE_VRINTf16Z:908 case MVE_VRINTf32A:909 case MVE_VRINTf32M:910 case MVE_VRINTf32N:911 case MVE_VRINTf32P:912 case MVE_VRINTf32X:913 case MVE_VRINTf32Z:914 case MVE_VRMULHs32:915 case MVE_VRMULHs16:916 case MVE_VRMULHs8:917 case MVE_VRMULHu32:918 case MVE_VRMULHu16:919 case MVE_VRMULHu8:920 case MVE_VRSHL_by_vecs16:921 case MVE_VRSHL_by_vecs32:922 case MVE_VRSHL_by_vecs8:923 case MVE_VRSHL_by_vecu16:924 case MVE_VRSHL_by_vecu32:925 case MVE_VRSHL_by_vecu8:926 case MVE_VRSHL_qrs16:927 case MVE_VRSHL_qrs32:928 case MVE_VRSHL_qrs8:929 case MVE_VRSHL_qru16:930 case MVE_VRSHL_qru32:931 case MVE_VRSHL_qru8:932 case MVE_VRSHR_imms16:933 case MVE_VRSHR_imms32:934 case MVE_VRSHR_imms8:935 case MVE_VRSHR_immu16:936 case MVE_VRSHR_immu32:937 case MVE_VRSHR_immu8:938 case MVE_VRSHRNi16bh:939 case MVE_VRSHRNi16th:940 case MVE_VRSHRNi32bh:941 case MVE_VRSHRNi32th:942 case MVE_VSHL_by_vecs16:943 case MVE_VSHL_by_vecs32:944 case MVE_VSHL_by_vecs8:945 case MVE_VSHL_by_vecu16:946 case MVE_VSHL_by_vecu32:947 case MVE_VSHL_by_vecu8:948 case MVE_VSHL_immi16:949 case MVE_VSHL_immi32:950 case MVE_VSHL_immi8:951 case MVE_VSHL_qrs16:952 case MVE_VSHL_qrs32:953 case MVE_VSHL_qrs8:954 case MVE_VSHL_qru16:955 case MVE_VSHL_qru32:956 case MVE_VSHL_qru8:957 case MVE_VSHR_imms16:958 case MVE_VSHR_imms32:959 case MVE_VSHR_imms8:960 case MVE_VSHR_immu16:961 case MVE_VSHR_immu32:962 case MVE_VSHR_immu8:963 case MVE_VSHRNi16bh:964 case MVE_VSHRNi16th:965 case MVE_VSHRNi32bh:966 case MVE_VSHRNi32th:967 case MVE_VSLIimm16:968 case MVE_VSLIimm32:969 case MVE_VSLIimm8:970 case MVE_VSRIimm16:971 case MVE_VSRIimm32:972 case MVE_VSRIimm8:973 case MVE_VSTRB16:974 case MVE_VSTRB16_post:975 case MVE_VSTRB16_pre:976 case MVE_VSTRB16_rq:977 case MVE_VSTRB32:978 case MVE_VSTRB32_post:979 case MVE_VSTRB32_pre:980 case MVE_VSTRB32_rq:981 case MVE_VSTRB8_rq:982 case MVE_VSTRBU8:983 case MVE_VSTRBU8_post:984 case MVE_VSTRBU8_pre:985 case MVE_VSTRD64_qi:986 case MVE_VSTRD64_qi_pre:987 case MVE_VSTRD64_rq:988 case MVE_VSTRD64_rq_u:989 case MVE_VSTRH16_rq:990 case MVE_VSTRH16_rq_u:991 case MVE_VSTRH32:992 case MVE_VSTRH32_post:993 case MVE_VSTRH32_pre:994 case MVE_VSTRH32_rq:995 case MVE_VSTRH32_rq_u:996 case MVE_VSTRHU16:997 case MVE_VSTRHU16_post:998 case MVE_VSTRHU16_pre:999 case MVE_VSTRW32_qi:1000 case MVE_VSTRW32_qi_pre:1001 case MVE_VSTRW32_rq:1002 case MVE_VSTRW32_rq_u:1003 case MVE_VSTRWU32:1004 case MVE_VSTRWU32_post:1005 case MVE_VSTRWU32_pre:1006 case MVE_VSUB_qr_f16:1007 case MVE_VSUB_qr_f32:1008 case MVE_VSUB_qr_i16:1009 case MVE_VSUB_qr_i32:1010 case MVE_VSUB_qr_i8:1011 case MVE_VSUBf16:1012 case MVE_VSUBf32:1013 case MVE_VSUBi16:1014 case MVE_VSUBi32:1015 case MVE_VSUBi8:1016 case VLDR_P0_off:1017 case VLDR_P0_post:1018 case VLDR_P0_pre:1019 case VLDR_VPR_off:1020 case VLDR_VPR_post:1021 case VLDR_VPR_pre:1022 case VSTR_P0_off:1023 case VSTR_P0_post:1024 case VSTR_P0_pre:1025 case VSTR_VPR_off:1026 case VSTR_VPR_post:1027 case VSTR_VPR_pre:1028 case VMRS_P0:1029 case VMRS_VPR:1030 return true;1031 }1032 };1033 1034 LLVMInitializeARMTargetInfo();1035 LLVMInitializeARMTarget();1036 LLVMInitializeARMTargetMC();1037 1038 Triple TT("thumbv8.1m.main-none-none-eabi");1039 std::string Error;1040 const Target *T = TargetRegistry::lookupTarget(TT, Error);1041 if (!T) {1042 dbgs() << Error;1043 GTEST_SKIP();1044 }1045 1046 TargetOptions Options;1047 auto TM = std::unique_ptr<TargetMachine>(1048 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,1049 std::nullopt, CodeGenOptLevel::Default));1050 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),1051 std::string(TM->getTargetFeatureString()),1052 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);1053 1054 auto MII = TM->getMCInstrInfo();1055 for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {1056 uint64_t Flags = MII->get(i).TSFlags;1057 if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)1058 continue;1059 bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;1060 ASSERT_EQ(IsValidTPOpcode(i), Valid)1061 << MII->getName(i)1062 << ": mismatched expectation for tail-predicated safety\n";1063 }1064}1065 1066TEST(MachineInstr, HasSideEffects) {1067 using namespace ARM;1068 std::set<unsigned> UnpredictableOpcodes = {1069 // MVE Instructions1070 MVE_VCTP8,1071 MVE_VCTP16,1072 MVE_VCTP32,1073 MVE_VCTP64,1074 MVE_VPST,1075 MVE_VPTv16i8,1076 MVE_VPTv8i16,1077 MVE_VPTv4i32,1078 MVE_VPTv16i8r,1079 MVE_VPTv8i16r,1080 MVE_VPTv4i32r,1081 MVE_VPTv16s8,1082 MVE_VPTv8s16,1083 MVE_VPTv4s32,1084 MVE_VPTv16s8r,1085 MVE_VPTv8s16r,1086 MVE_VPTv4s32r,1087 MVE_VPTv16u8,1088 MVE_VPTv8u16,1089 MVE_VPTv4u32,1090 MVE_VPTv16u8r,1091 MVE_VPTv8u16r,1092 MVE_VPTv4u32r,1093 MVE_VPTv8f16,1094 MVE_VPTv4f32,1095 MVE_VPTv8f16r,1096 MVE_VPTv4f32r,1097 MVE_VADC,1098 MVE_VADCI,1099 MVE_VSBC,1100 MVE_VSBCI,1101 MVE_VSHLC,1102 // FP Instructions1103 FLDMXIA,1104 FLDMXDB_UPD,1105 FLDMXIA_UPD,1106 FSTMXDB_UPD,1107 FSTMXIA,1108 FSTMXIA_UPD,1109 VLDR_FPCXTNS_off,1110 VLDR_FPCXTNS_off,1111 VLDR_FPCXTNS_post,1112 VLDR_FPCXTNS_pre,1113 VLDR_FPCXTS_off,1114 VLDR_FPCXTS_post,1115 VLDR_FPCXTS_pre,1116 VLDR_FPSCR_NZCVQC_off,1117 VLDR_FPSCR_NZCVQC_post,1118 VLDR_FPSCR_NZCVQC_pre,1119 VLDR_FPSCR_off,1120 VLDR_FPSCR_post,1121 VLDR_FPSCR_pre,1122 VLDR_P0_off,1123 VLDR_P0_post,1124 VLDR_P0_pre,1125 VLDR_VPR_off,1126 VLDR_VPR_post,1127 VLDR_VPR_pre,1128 VLLDM,1129 VLLDM_T2,1130 VLSTM,1131 VLSTM_T2,1132 VMRS,1133 VMRS_FPCXTNS,1134 VMRS_FPCXTS,1135 VMRS_FPEXC,1136 VMRS_FPINST,1137 VMRS_FPINST2,1138 VMRS_FPSCR_NZCVQC,1139 VMRS_FPSID,1140 VMRS_MVFR0,1141 VMRS_MVFR1,1142 VMRS_MVFR2,1143 VMRS_P0,1144 VMRS_VPR,1145 VMSR,1146 VMSR_FPCXTNS,1147 VMSR_FPCXTS,1148 VMSR_FPEXC,1149 VMSR_FPINST,1150 VMSR_FPINST2,1151 VMSR_FPSCR_NZCVQC,1152 VMSR_FPSID,1153 VMSR_P0,1154 VMSR_VPR,1155 VSCCLRMD,1156 VSCCLRMS,1157 VSTR_FPCXTNS_off,1158 VSTR_FPCXTNS_post,1159 VSTR_FPCXTNS_pre,1160 VSTR_FPCXTS_off,1161 VSTR_FPCXTS_post,1162 VSTR_FPCXTS_pre,1163 VSTR_FPSCR_NZCVQC_off,1164 VSTR_FPSCR_NZCVQC_post,1165 VSTR_FPSCR_NZCVQC_pre,1166 VSTR_FPSCR_off,1167 VSTR_FPSCR_post,1168 VSTR_FPSCR_pre,1169 VSTR_P0_off,1170 VSTR_P0_post,1171 VSTR_P0_pre,1172 VSTR_VPR_off,1173 VSTR_VPR_post,1174 VSTR_VPR_pre,1175 };1176 1177 LLVMInitializeARMTargetInfo();1178 LLVMInitializeARMTarget();1179 LLVMInitializeARMTargetMC();1180 1181 Triple TT("thumbv8.1m.main-none-none-eabi");1182 std::string Error;1183 const Target *T = TargetRegistry::lookupTarget(TT, Error);1184 if (!T) {1185 dbgs() << Error;1186 GTEST_SKIP();1187 }1188 1189 TargetOptions Options;1190 auto TM = std::unique_ptr<TargetMachine>(1191 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,1192 std::nullopt, CodeGenOptLevel::Default));1193 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),1194 std::string(TM->getTargetFeatureString()),1195 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);1196 const ARMBaseInstrInfo *TII = ST.getInstrInfo();1197 auto MII = TM->getMCInstrInfo();1198 1199 for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {1200 const MCInstrDesc &Desc = TII->get(Op);1201 if ((Desc.TSFlags &1202 (ARMII::DomainMVE | ARMII::DomainVFP | ARMII::DomainNEONA8)) == 0)1203 continue;1204 if (UnpredictableOpcodes.count(Op))1205 continue;1206 1207 ASSERT_FALSE(Desc.hasUnmodeledSideEffects())1208 << MII->getName(Op) << " has unexpected side effects";1209 }1210}1211 1212TEST(MachineInstr, MVEVecSize) {1213 using namespace ARM;1214 auto MVEVecSize = [](unsigned Opcode) {1215 switch (Opcode) {1216 default:1217 dbgs() << Opcode << "\n";1218 llvm_unreachable("Unexpected MVE instruction!");1219 case MVE_ASRLi:1220 case MVE_ASRLr:1221 case MVE_LSLLi:1222 case MVE_LSLLr:1223 case MVE_LSRL:1224 case MVE_SQRSHR:1225 case MVE_SQRSHRL:1226 case MVE_SQSHL:1227 case MVE_SQSHLL:1228 case MVE_SRSHR:1229 case MVE_SRSHRL:1230 case MVE_UQRSHL:1231 case MVE_UQRSHLL:1232 case MVE_UQSHL:1233 case MVE_UQSHLL:1234 case MVE_URSHR:1235 case MVE_URSHRL:1236 case MVE_VABAVs8:1237 case MVE_VABAVu8:1238 case MVE_VABDs8:1239 case MVE_VABDu8:1240 case MVE_VABSs8:1241 case MVE_VADDVs8acc:1242 case MVE_VADDVs8no_acc:1243 case MVE_VADDVu8acc:1244 case MVE_VADDVu8no_acc:1245 case MVE_VADD_qr_i8:1246 case MVE_VADDi8:1247 case MVE_VBRSR8:1248 case MVE_VCADDi8:1249 case MVE_VCLSs8:1250 case MVE_VCLZs8:1251 case MVE_VCMPi8:1252 case MVE_VCMPi8r:1253 case MVE_VCMPs8:1254 case MVE_VCMPs8r:1255 case MVE_VCMPu8:1256 case MVE_VCMPu8r:1257 case MVE_VCTP8:1258 case MVE_VDDUPu8:1259 case MVE_VDUP8:1260 case MVE_VDWDUPu8:1261 case MVE_VHADD_qr_s8:1262 case MVE_VHADD_qr_u8:1263 case MVE_VHADDs8:1264 case MVE_VHADDu8:1265 case MVE_VHCADDs8:1266 case MVE_VHSUB_qr_s8:1267 case MVE_VHSUB_qr_u8:1268 case MVE_VHSUBs8:1269 case MVE_VHSUBu8:1270 case MVE_VIDUPu8:1271 case MVE_VIWDUPu8:1272 case MVE_VLD20_8:1273 case MVE_VLD20_8_wb:1274 case MVE_VLD21_8:1275 case MVE_VLD21_8_wb:1276 case MVE_VLD40_8:1277 case MVE_VLD40_8_wb:1278 case MVE_VLD41_8:1279 case MVE_VLD41_8_wb:1280 case MVE_VLD42_8:1281 case MVE_VLD42_8_wb:1282 case MVE_VLD43_8:1283 case MVE_VLD43_8_wb:1284 case MVE_VLDRBU8:1285 case MVE_VLDRBU8_post:1286 case MVE_VLDRBU8_pre:1287 case MVE_VLDRBU8_rq:1288 case MVE_VMAXAVs8:1289 case MVE_VMAXAs8:1290 case MVE_VMAXVs8:1291 case MVE_VMAXVu8:1292 case MVE_VMAXs8:1293 case MVE_VMAXu8:1294 case MVE_VMINAVs8:1295 case MVE_VMINAs8:1296 case MVE_VMINVs8:1297 case MVE_VMINVu8:1298 case MVE_VMINs8:1299 case MVE_VMINu8:1300 case MVE_VMLADAVas8:1301 case MVE_VMLADAVau8:1302 case MVE_VMLADAVaxs8:1303 case MVE_VMLADAVs8:1304 case MVE_VMLADAVu8:1305 case MVE_VMLADAVxs8:1306 case MVE_VMLAS_qr_i8:1307 case MVE_VMLA_qr_i8:1308 case MVE_VMLSDAVas8:1309 case MVE_VMLSDAVaxs8:1310 case MVE_VMLSDAVs8:1311 case MVE_VMLSDAVxs8:1312 case MVE_VMOV_from_lane_s8:1313 case MVE_VMOV_from_lane_u8:1314 case MVE_VMOV_to_lane_8:1315 case MVE_VMOVimmi8:1316 case MVE_VMULHs8:1317 case MVE_VMULHu8:1318 case MVE_VMUL_qr_i8:1319 case MVE_VMULi8:1320 case MVE_VNEGs8:1321 case MVE_VPTv16i8:1322 case MVE_VPTv16i8r:1323 case MVE_VPTv16s8:1324 case MVE_VPTv16s8r:1325 case MVE_VPTv16u8:1326 case MVE_VPTv16u8r:1327 case MVE_VQABSs8:1328 case MVE_VQADD_qr_s8:1329 case MVE_VQADD_qr_u8:1330 case MVE_VQADDs8:1331 case MVE_VQADDu8:1332 case MVE_VQDMLADHXs8:1333 case MVE_VQDMLADHs8:1334 case MVE_VQDMLAH_qrs8:1335 case MVE_VQDMLASH_qrs8:1336 case MVE_VQDMLSDHXs8:1337 case MVE_VQDMLSDHs8:1338 case MVE_VQDMULH_qr_s8:1339 case MVE_VQDMULHi8:1340 case MVE_VQNEGs8:1341 case MVE_VQRDMLADHXs8:1342 case MVE_VQRDMLADHs8:1343 case MVE_VQRDMLAH_qrs8:1344 case MVE_VQRDMLASH_qrs8:1345 case MVE_VQRDMLSDHXs8:1346 case MVE_VQRDMLSDHs8:1347 case MVE_VQRDMULH_qr_s8:1348 case MVE_VQRDMULHi8:1349 case MVE_VQRSHL_by_vecs8:1350 case MVE_VQRSHL_by_vecu8:1351 case MVE_VQRSHL_qrs8:1352 case MVE_VQRSHL_qru8:1353 case MVE_VQSHLU_imms8:1354 case MVE_VQSHL_by_vecs8:1355 case MVE_VQSHL_by_vecu8:1356 case MVE_VQSHL_qrs8:1357 case MVE_VQSHL_qru8:1358 case MVE_VQSHLimms8:1359 case MVE_VQSHLimmu8:1360 case MVE_VQSUB_qr_s8:1361 case MVE_VQSUB_qr_u8:1362 case MVE_VQSUBs8:1363 case MVE_VQSUBu8:1364 case MVE_VRHADDs8:1365 case MVE_VRHADDu8:1366 case MVE_VRMULHs8:1367 case MVE_VRMULHu8:1368 case MVE_VRSHL_by_vecs8:1369 case MVE_VRSHL_by_vecu8:1370 case MVE_VRSHL_qrs8:1371 case MVE_VRSHL_qru8:1372 case MVE_VRSHR_imms8:1373 case MVE_VRSHR_immu8:1374 case MVE_VSHL_by_vecs8:1375 case MVE_VSHL_by_vecu8:1376 case MVE_VSHL_immi8:1377 case MVE_VSHL_qru8:1378 case MVE_VSHL_qrs8:1379 case MVE_VSHR_imms8:1380 case MVE_VSHR_immu8:1381 case MVE_VSLIimm8:1382 case MVE_VSRIimm8:1383 case MVE_VST20_8:1384 case MVE_VST20_8_wb:1385 case MVE_VST21_8:1386 case MVE_VST21_8_wb:1387 case MVE_VST40_8:1388 case MVE_VST40_8_wb:1389 case MVE_VST41_8:1390 case MVE_VST41_8_wb:1391 case MVE_VST42_8:1392 case MVE_VST42_8_wb:1393 case MVE_VST43_8:1394 case MVE_VST43_8_wb:1395 case MVE_VSTRB8_rq:1396 case MVE_VSTRBU8:1397 case MVE_VSTRBU8_post:1398 case MVE_VSTRBU8_pre:1399 case MVE_VSUB_qr_i8:1400 case MVE_VSUBi8:1401 case MVE_VAND:1402 case MVE_VBIC:1403 case MVE_VEOR:1404 case MVE_VMVN:1405 case MVE_VORN:1406 case MVE_VORR:1407 case MVE_VPNOT:1408 case MVE_VPSEL:1409 case MVE_VPST:1410 case MQPRCopy:1411 return 0;1412 case MVE_VABAVs16:1413 case MVE_VABAVu16:1414 case MVE_VABDf16:1415 case MVE_VABDs16:1416 case MVE_VABDu16:1417 case MVE_VABSf16:1418 case MVE_VABSs16:1419 case MVE_VADDVs16acc:1420 case MVE_VADDVs16no_acc:1421 case MVE_VADDVu16acc:1422 case MVE_VADDVu16no_acc:1423 case MVE_VADD_qr_f16:1424 case MVE_VADD_qr_i16:1425 case MVE_VADDf16:1426 case MVE_VADDi16:1427 case MVE_VBICimmi16:1428 case MVE_VBRSR16:1429 case MVE_VCADDf16:1430 case MVE_VCADDi16:1431 case MVE_VCLSs16:1432 case MVE_VCLZs16:1433 case MVE_VCMLAf16:1434 case MVE_VCMPf16:1435 case MVE_VCMPf16r:1436 case MVE_VCMPi16:1437 case MVE_VCMPi16r:1438 case MVE_VCMPs16:1439 case MVE_VCMPs16r:1440 case MVE_VCMPu16:1441 case MVE_VCMPu16r:1442 case MVE_VCMULf16:1443 case MVE_VCTP16:1444 case MVE_VCVTf16s16_fix:1445 case MVE_VCVTf16s16n:1446 case MVE_VCVTf16u16_fix:1447 case MVE_VCVTf16u16n:1448 case MVE_VCVTs16f16_fix:1449 case MVE_VCVTs16f16a:1450 case MVE_VCVTs16f16m:1451 case MVE_VCVTs16f16n:1452 case MVE_VCVTs16f16p:1453 case MVE_VCVTs16f16z:1454 case MVE_VCVTu16f16_fix:1455 case MVE_VCVTu16f16a:1456 case MVE_VCVTu16f16m:1457 case MVE_VCVTu16f16n:1458 case MVE_VCVTu16f16p:1459 case MVE_VCVTu16f16z:1460 case MVE_VDDUPu16:1461 case MVE_VDUP16:1462 case MVE_VDWDUPu16:1463 case MVE_VFMA_qr_Sf16:1464 case MVE_VFMA_qr_f16:1465 case MVE_VFMAf16:1466 case MVE_VFMSf16:1467 case MVE_VHADD_qr_s16:1468 case MVE_VHADD_qr_u16:1469 case MVE_VHADDs16:1470 case MVE_VHADDu16:1471 case MVE_VHCADDs16:1472 case MVE_VHSUB_qr_s16:1473 case MVE_VHSUB_qr_u16:1474 case MVE_VHSUBs16:1475 case MVE_VHSUBu16:1476 case MVE_VIDUPu16:1477 case MVE_VIWDUPu16:1478 case MVE_VLD20_16:1479 case MVE_VLD20_16_wb:1480 case MVE_VLD21_16:1481 case MVE_VLD21_16_wb:1482 case MVE_VLD40_16:1483 case MVE_VLD40_16_wb:1484 case MVE_VLD41_16:1485 case MVE_VLD41_16_wb:1486 case MVE_VLD42_16:1487 case MVE_VLD42_16_wb:1488 case MVE_VLD43_16:1489 case MVE_VLD43_16_wb:1490 case MVE_VLDRBS16:1491 case MVE_VLDRBS16_post:1492 case MVE_VLDRBS16_pre:1493 case MVE_VLDRBS16_rq:1494 case MVE_VLDRBU16:1495 case MVE_VLDRBU16_post:1496 case MVE_VLDRBU16_pre:1497 case MVE_VLDRBU16_rq:1498 case MVE_VLDRHU16:1499 case MVE_VLDRHU16_post:1500 case MVE_VLDRHU16_pre:1501 case MVE_VLDRHU16_rq:1502 case MVE_VLDRHU16_rq_u:1503 case MVE_VMAXAVs16:1504 case MVE_VMAXAs16:1505 case MVE_VMAXNMAVf16:1506 case MVE_VMAXNMAf16:1507 case MVE_VMAXNMVf16:1508 case MVE_VMAXNMf16:1509 case MVE_VMAXVs16:1510 case MVE_VMAXVu16:1511 case MVE_VMAXs16:1512 case MVE_VMAXu16:1513 case MVE_VMINAVs16:1514 case MVE_VMINAs16:1515 case MVE_VMINNMAVf16:1516 case MVE_VMINNMAf16:1517 case MVE_VMINNMVf16:1518 case MVE_VMINNMf16:1519 case MVE_VMINVs16:1520 case MVE_VMINVu16:1521 case MVE_VMINs16:1522 case MVE_VMINu16:1523 case MVE_VMLADAVas16:1524 case MVE_VMLADAVau16:1525 case MVE_VMLADAVaxs16:1526 case MVE_VMLADAVs16:1527 case MVE_VMLADAVu16:1528 case MVE_VMLADAVxs16:1529 case MVE_VMLALDAVas16:1530 case MVE_VMLALDAVau16:1531 case MVE_VMLALDAVaxs16:1532 case MVE_VMLALDAVs16:1533 case MVE_VMLALDAVu16:1534 case MVE_VMLALDAVxs16:1535 case MVE_VMLAS_qr_i16:1536 case MVE_VMLA_qr_i16:1537 case MVE_VMLSDAVas16:1538 case MVE_VMLSDAVaxs16:1539 case MVE_VMLSDAVs16:1540 case MVE_VMLSDAVxs16:1541 case MVE_VMLSLDAVas16:1542 case MVE_VMLSLDAVaxs16:1543 case MVE_VMLSLDAVs16:1544 case MVE_VMLSLDAVxs16:1545 case MVE_VMOVNi16bh:1546 case MVE_VMOVNi16th:1547 case MVE_VMOV_from_lane_s16:1548 case MVE_VMOV_from_lane_u16:1549 case MVE_VMOV_to_lane_16:1550 case MVE_VMOVimmi16:1551 case MVE_VMOVLs8bh:1552 case MVE_VMOVLs8th:1553 case MVE_VMOVLu8bh:1554 case MVE_VMOVLu8th:1555 case MVE_VMULLBp8:1556 case MVE_VMULLBs8:1557 case MVE_VMULLBu8:1558 case MVE_VMULLTp8:1559 case MVE_VMULLTs8:1560 case MVE_VMULLTu8:1561 case MVE_VMULHs16:1562 case MVE_VMULHu16:1563 case MVE_VMUL_qr_f16:1564 case MVE_VMUL_qr_i16:1565 case MVE_VMULf16:1566 case MVE_VMULi16:1567 case MVE_VMVNimmi16:1568 case MVE_VNEGf16:1569 case MVE_VNEGs16:1570 case MVE_VORRimmi16:1571 case MVE_VPTv8f16:1572 case MVE_VPTv8f16r:1573 case MVE_VPTv8i16:1574 case MVE_VPTv8i16r:1575 case MVE_VPTv8s16:1576 case MVE_VPTv8s16r:1577 case MVE_VPTv8u16:1578 case MVE_VPTv8u16r:1579 case MVE_VQABSs16:1580 case MVE_VQADD_qr_s16:1581 case MVE_VQADD_qr_u16:1582 case MVE_VQADDs16:1583 case MVE_VQADDu16:1584 case MVE_VQDMLADHXs16:1585 case MVE_VQDMLADHs16:1586 case MVE_VQDMLAH_qrs16:1587 case MVE_VQDMLASH_qrs16:1588 case MVE_VQDMLSDHXs16:1589 case MVE_VQDMLSDHs16:1590 case MVE_VQDMULH_qr_s16:1591 case MVE_VQDMULHi16:1592 case MVE_VQDMULL_qr_s16bh:1593 case MVE_VQDMULL_qr_s16th:1594 case MVE_VQDMULLs16bh:1595 case MVE_VQDMULLs16th:1596 case MVE_VQMOVNs16bh:1597 case MVE_VQMOVNs16th:1598 case MVE_VQMOVNu16bh:1599 case MVE_VQMOVNu16th:1600 case MVE_VQMOVUNs16bh:1601 case MVE_VQMOVUNs16th:1602 case MVE_VQNEGs16:1603 case MVE_VQRDMLADHXs16:1604 case MVE_VQRDMLADHs16:1605 case MVE_VQRDMLAH_qrs16:1606 case MVE_VQRDMLASH_qrs16:1607 case MVE_VQRDMLSDHXs16:1608 case MVE_VQRDMLSDHs16:1609 case MVE_VQRDMULH_qr_s16:1610 case MVE_VQRDMULHi16:1611 case MVE_VQRSHL_by_vecs16:1612 case MVE_VQRSHL_by_vecu16:1613 case MVE_VQRSHL_qrs16:1614 case MVE_VQRSHL_qru16:1615 case MVE_VQRSHRNbhs16:1616 case MVE_VQRSHRNbhu16:1617 case MVE_VQRSHRNths16:1618 case MVE_VQRSHRNthu16:1619 case MVE_VQRSHRUNs16bh:1620 case MVE_VQRSHRUNs16th:1621 case MVE_VQSHLU_imms16:1622 case MVE_VQSHL_by_vecs16:1623 case MVE_VQSHL_by_vecu16:1624 case MVE_VQSHL_qrs16:1625 case MVE_VQSHL_qru16:1626 case MVE_VQSHLimms16:1627 case MVE_VQSHLimmu16:1628 case MVE_VQSHRNbhs16:1629 case MVE_VQSHRNbhu16:1630 case MVE_VQSHRNths16:1631 case MVE_VQSHRNthu16:1632 case MVE_VQSHRUNs16bh:1633 case MVE_VQSHRUNs16th:1634 case MVE_VQSUB_qr_s16:1635 case MVE_VQSUB_qr_u16:1636 case MVE_VQSUBs16:1637 case MVE_VQSUBu16:1638 case MVE_VREV16_8:1639 case MVE_VRHADDs16:1640 case MVE_VRHADDu16:1641 case MVE_VRINTf16A:1642 case MVE_VRINTf16M:1643 case MVE_VRINTf16N:1644 case MVE_VRINTf16P:1645 case MVE_VRINTf16X:1646 case MVE_VRINTf16Z:1647 case MVE_VRMULHs16:1648 case MVE_VRMULHu16:1649 case MVE_VRSHL_by_vecs16:1650 case MVE_VRSHL_by_vecu16:1651 case MVE_VRSHL_qrs16:1652 case MVE_VRSHL_qru16:1653 case MVE_VRSHRNi16bh:1654 case MVE_VRSHRNi16th:1655 case MVE_VRSHR_imms16:1656 case MVE_VRSHR_immu16:1657 case MVE_VSHLL_imms8bh:1658 case MVE_VSHLL_imms8th:1659 case MVE_VSHLL_immu8bh:1660 case MVE_VSHLL_immu8th:1661 case MVE_VSHLL_lws8bh:1662 case MVE_VSHLL_lws8th:1663 case MVE_VSHLL_lwu8bh:1664 case MVE_VSHLL_lwu8th:1665 case MVE_VSHL_by_vecs16:1666 case MVE_VSHL_by_vecu16:1667 case MVE_VSHL_immi16:1668 case MVE_VSHL_qrs16:1669 case MVE_VSHL_qru16:1670 case MVE_VSHRNi16bh:1671 case MVE_VSHRNi16th:1672 case MVE_VSHR_imms16:1673 case MVE_VSHR_immu16:1674 case MVE_VSLIimm16:1675 case MVE_VSRIimm16:1676 case MVE_VST20_16:1677 case MVE_VST20_16_wb:1678 case MVE_VST21_16:1679 case MVE_VST21_16_wb:1680 case MVE_VST40_16:1681 case MVE_VST40_16_wb:1682 case MVE_VST41_16:1683 case MVE_VST41_16_wb:1684 case MVE_VST42_16:1685 case MVE_VST42_16_wb:1686 case MVE_VST43_16:1687 case MVE_VST43_16_wb:1688 case MVE_VSTRB16:1689 case MVE_VSTRB16_post:1690 case MVE_VSTRB16_pre:1691 case MVE_VSTRB16_rq:1692 case MVE_VSTRH16_rq:1693 case MVE_VSTRH16_rq_u:1694 case MVE_VSTRHU16:1695 case MVE_VSTRHU16_post:1696 case MVE_VSTRHU16_pre:1697 case MVE_VSUB_qr_f16:1698 case MVE_VSUB_qr_i16:1699 case MVE_VSUBf16:1700 case MVE_VSUBi16:1701 return 1;1702 case MVE_VABAVs32:1703 case MVE_VABAVu32:1704 case MVE_VABDf32:1705 case MVE_VABDs32:1706 case MVE_VABDu32:1707 case MVE_VABSf32:1708 case MVE_VABSs32:1709 case MVE_VADC:1710 case MVE_VADCI:1711 case MVE_VADDLVs32acc:1712 case MVE_VADDLVs32no_acc:1713 case MVE_VADDLVu32acc:1714 case MVE_VADDLVu32no_acc:1715 case MVE_VADDVs32acc:1716 case MVE_VADDVs32no_acc:1717 case MVE_VADDVu32acc:1718 case MVE_VADDVu32no_acc:1719 case MVE_VADD_qr_f32:1720 case MVE_VADD_qr_i32:1721 case MVE_VADDf32:1722 case MVE_VADDi32:1723 case MVE_VBICimmi32:1724 case MVE_VBRSR32:1725 case MVE_VCADDf32:1726 case MVE_VCADDi32:1727 case MVE_VCLSs32:1728 case MVE_VCLZs32:1729 case MVE_VCMLAf32:1730 case MVE_VCMPf32:1731 case MVE_VCMPf32r:1732 case MVE_VCMPi32:1733 case MVE_VCMPi32r:1734 case MVE_VCMPs32:1735 case MVE_VCMPs32r:1736 case MVE_VCMPu32:1737 case MVE_VCMPu32r:1738 case MVE_VCMULf32:1739 case MVE_VCTP32:1740 case MVE_VCVTf16f32bh:1741 case MVE_VCVTf16f32th:1742 case MVE_VCVTf32f16bh:1743 case MVE_VCVTf32f16th:1744 case MVE_VCVTf32s32_fix:1745 case MVE_VCVTf32s32n:1746 case MVE_VCVTf32u32_fix:1747 case MVE_VCVTf32u32n:1748 case MVE_VCVTs32f32_fix:1749 case MVE_VCVTs32f32a:1750 case MVE_VCVTs32f32m:1751 case MVE_VCVTs32f32n:1752 case MVE_VCVTs32f32p:1753 case MVE_VCVTs32f32z:1754 case MVE_VCVTu32f32_fix:1755 case MVE_VCVTu32f32a:1756 case MVE_VCVTu32f32m:1757 case MVE_VCVTu32f32n:1758 case MVE_VCVTu32f32p:1759 case MVE_VCVTu32f32z:1760 case MVE_VDDUPu32:1761 case MVE_VDUP32:1762 case MVE_VDWDUPu32:1763 case MVE_VFMA_qr_Sf32:1764 case MVE_VFMA_qr_f32:1765 case MVE_VFMAf32:1766 case MVE_VFMSf32:1767 case MVE_VHADD_qr_s32:1768 case MVE_VHADD_qr_u32:1769 case MVE_VHADDs32:1770 case MVE_VHADDu32:1771 case MVE_VHCADDs32:1772 case MVE_VHSUB_qr_s32:1773 case MVE_VHSUB_qr_u32:1774 case MVE_VHSUBs32:1775 case MVE_VHSUBu32:1776 case MVE_VIDUPu32:1777 case MVE_VIWDUPu32:1778 case MVE_VLD20_32:1779 case MVE_VLD20_32_wb:1780 case MVE_VLD21_32:1781 case MVE_VLD21_32_wb:1782 case MVE_VLD40_32:1783 case MVE_VLD40_32_wb:1784 case MVE_VLD41_32:1785 case MVE_VLD41_32_wb:1786 case MVE_VLD42_32:1787 case MVE_VLD42_32_wb:1788 case MVE_VLD43_32:1789 case MVE_VLD43_32_wb:1790 case MVE_VLDRBS32:1791 case MVE_VLDRBS32_post:1792 case MVE_VLDRBS32_pre:1793 case MVE_VLDRBS32_rq:1794 case MVE_VLDRBU32:1795 case MVE_VLDRBU32_post:1796 case MVE_VLDRBU32_pre:1797 case MVE_VLDRBU32_rq:1798 case MVE_VLDRHS32:1799 case MVE_VLDRHS32_post:1800 case MVE_VLDRHS32_pre:1801 case MVE_VLDRHS32_rq:1802 case MVE_VLDRHS32_rq_u:1803 case MVE_VLDRHU32:1804 case MVE_VLDRHU32_post:1805 case MVE_VLDRHU32_pre:1806 case MVE_VLDRHU32_rq:1807 case MVE_VLDRHU32_rq_u:1808 case MVE_VLDRWU32:1809 case MVE_VLDRWU32_post:1810 case MVE_VLDRWU32_pre:1811 case MVE_VLDRWU32_qi:1812 case MVE_VLDRWU32_qi_pre:1813 case MVE_VLDRWU32_rq:1814 case MVE_VLDRWU32_rq_u:1815 case MVE_VMAXAVs32:1816 case MVE_VMAXAs32:1817 case MVE_VMAXNMAVf32:1818 case MVE_VMAXNMAf32:1819 case MVE_VMAXNMVf32:1820 case MVE_VMAXNMf32:1821 case MVE_VMAXVs32:1822 case MVE_VMAXVu32:1823 case MVE_VMAXs32:1824 case MVE_VMAXu32:1825 case MVE_VMINAVs32:1826 case MVE_VMINAs32:1827 case MVE_VMINNMAVf32:1828 case MVE_VMINNMAf32:1829 case MVE_VMINNMVf32:1830 case MVE_VMINNMf32:1831 case MVE_VMINVs32:1832 case MVE_VMINVu32:1833 case MVE_VMINs32:1834 case MVE_VMINu32:1835 case MVE_VMLADAVas32:1836 case MVE_VMLADAVau32:1837 case MVE_VMLADAVaxs32:1838 case MVE_VMLADAVs32:1839 case MVE_VMLADAVu32:1840 case MVE_VMLADAVxs32:1841 case MVE_VMLALDAVas32:1842 case MVE_VMLALDAVau32:1843 case MVE_VMLALDAVaxs32:1844 case MVE_VMLALDAVs32:1845 case MVE_VMLALDAVu32:1846 case MVE_VMLALDAVxs32:1847 case MVE_VMLAS_qr_i32:1848 case MVE_VMLA_qr_i32:1849 case MVE_VMLSDAVas32:1850 case MVE_VMLSDAVaxs32:1851 case MVE_VMLSDAVs32:1852 case MVE_VMLSDAVxs32:1853 case MVE_VMLSLDAVas32:1854 case MVE_VMLSLDAVaxs32:1855 case MVE_VMLSLDAVs32:1856 case MVE_VMLSLDAVxs32:1857 case MVE_VMOVNi32bh:1858 case MVE_VMOVNi32th:1859 case MVE_VMOV_from_lane_32:1860 case MVE_VMOV_q_rr:1861 case MVE_VMOV_rr_q:1862 case MVE_VMOV_to_lane_32:1863 case MVE_VMOVimmf32:1864 case MVE_VMOVimmi32:1865 case MVE_VMOVLs16bh:1866 case MVE_VMOVLs16th:1867 case MVE_VMOVLu16bh:1868 case MVE_VMOVLu16th:1869 case MVE_VMULHs32:1870 case MVE_VMULHu32:1871 case MVE_VMULLBp16:1872 case MVE_VMULLBs16:1873 case MVE_VMULLBu16:1874 case MVE_VMULLTp16:1875 case MVE_VMULLTs16:1876 case MVE_VMULLTu16:1877 case MVE_VMUL_qr_f32:1878 case MVE_VMUL_qr_i32:1879 case MVE_VMULf32:1880 case MVE_VMULi32:1881 case MVE_VMVNimmi32:1882 case MVE_VNEGf32:1883 case MVE_VNEGs32:1884 case MVE_VORRimmi32:1885 case MVE_VPTv4f32:1886 case MVE_VPTv4f32r:1887 case MVE_VPTv4i32:1888 case MVE_VPTv4i32r:1889 case MVE_VPTv4s32:1890 case MVE_VPTv4s32r:1891 case MVE_VPTv4u32:1892 case MVE_VPTv4u32r:1893 case MVE_VQABSs32:1894 case MVE_VQADD_qr_s32:1895 case MVE_VQADD_qr_u32:1896 case MVE_VQADDs32:1897 case MVE_VQADDu32:1898 case MVE_VQDMLADHXs32:1899 case MVE_VQDMLADHs32:1900 case MVE_VQDMLAH_qrs32:1901 case MVE_VQDMLASH_qrs32:1902 case MVE_VQDMLSDHXs32:1903 case MVE_VQDMLSDHs32:1904 case MVE_VQDMULH_qr_s32:1905 case MVE_VQDMULHi32:1906 case MVE_VQDMULL_qr_s32bh:1907 case MVE_VQDMULL_qr_s32th:1908 case MVE_VQDMULLs32bh:1909 case MVE_VQDMULLs32th:1910 case MVE_VQMOVNs32bh:1911 case MVE_VQMOVNs32th:1912 case MVE_VQMOVNu32bh:1913 case MVE_VQMOVNu32th:1914 case MVE_VQMOVUNs32bh:1915 case MVE_VQMOVUNs32th:1916 case MVE_VQNEGs32:1917 case MVE_VQRDMLADHXs32:1918 case MVE_VQRDMLADHs32:1919 case MVE_VQRDMLAH_qrs32:1920 case MVE_VQRDMLASH_qrs32:1921 case MVE_VQRDMLSDHXs32:1922 case MVE_VQRDMLSDHs32:1923 case MVE_VQRDMULH_qr_s32:1924 case MVE_VQRDMULHi32:1925 case MVE_VQRSHL_by_vecs32:1926 case MVE_VQRSHL_by_vecu32:1927 case MVE_VQRSHL_qrs32:1928 case MVE_VQRSHL_qru32:1929 case MVE_VQRSHRNbhs32:1930 case MVE_VQRSHRNbhu32:1931 case MVE_VQRSHRNths32:1932 case MVE_VQRSHRNthu32:1933 case MVE_VQRSHRUNs32bh:1934 case MVE_VQRSHRUNs32th:1935 case MVE_VQSHLU_imms32:1936 case MVE_VQSHL_by_vecs32:1937 case MVE_VQSHL_by_vecu32:1938 case MVE_VQSHL_qrs32:1939 case MVE_VQSHL_qru32:1940 case MVE_VQSHLimms32:1941 case MVE_VQSHLimmu32:1942 case MVE_VQSHRNbhs32:1943 case MVE_VQSHRNbhu32:1944 case MVE_VQSHRNths32:1945 case MVE_VQSHRNthu32:1946 case MVE_VQSHRUNs32bh:1947 case MVE_VQSHRUNs32th:1948 case MVE_VQSUB_qr_s32:1949 case MVE_VQSUB_qr_u32:1950 case MVE_VQSUBs32:1951 case MVE_VQSUBu32:1952 case MVE_VREV32_16:1953 case MVE_VREV32_8:1954 case MVE_VRHADDs32:1955 case MVE_VRHADDu32:1956 case MVE_VRINTf32A:1957 case MVE_VRINTf32M:1958 case MVE_VRINTf32N:1959 case MVE_VRINTf32P:1960 case MVE_VRINTf32X:1961 case MVE_VRINTf32Z:1962 case MVE_VRMLALDAVHas32:1963 case MVE_VRMLALDAVHau32:1964 case MVE_VRMLALDAVHaxs32:1965 case MVE_VRMLALDAVHs32:1966 case MVE_VRMLALDAVHu32:1967 case MVE_VRMLALDAVHxs32:1968 case MVE_VRMLSLDAVHas32:1969 case MVE_VRMLSLDAVHaxs32:1970 case MVE_VRMLSLDAVHs32:1971 case MVE_VRMLSLDAVHxs32:1972 case MVE_VRMULHs32:1973 case MVE_VRMULHu32:1974 case MVE_VRSHL_by_vecs32:1975 case MVE_VRSHL_by_vecu32:1976 case MVE_VRSHL_qrs32:1977 case MVE_VRSHL_qru32:1978 case MVE_VRSHRNi32bh:1979 case MVE_VRSHRNi32th:1980 case MVE_VRSHR_imms32:1981 case MVE_VRSHR_immu32:1982 case MVE_VSBC:1983 case MVE_VSBCI:1984 case MVE_VSHLC:1985 case MVE_VSHLL_imms16bh:1986 case MVE_VSHLL_imms16th:1987 case MVE_VSHLL_immu16bh:1988 case MVE_VSHLL_immu16th:1989 case MVE_VSHLL_lws16bh:1990 case MVE_VSHLL_lws16th:1991 case MVE_VSHLL_lwu16bh:1992 case MVE_VSHLL_lwu16th:1993 case MVE_VSHL_by_vecs32:1994 case MVE_VSHL_by_vecu32:1995 case MVE_VSHL_immi32:1996 case MVE_VSHL_qrs32:1997 case MVE_VSHL_qru32:1998 case MVE_VSHRNi32bh:1999 case MVE_VSHRNi32th:2000 case MVE_VSHR_imms32:2001 case MVE_VSHR_immu32:2002 case MVE_VSLIimm32:2003 case MVE_VSRIimm32:2004 case MVE_VST20_32:2005 case MVE_VST20_32_wb:2006 case MVE_VST21_32:2007 case MVE_VST21_32_wb:2008 case MVE_VST40_32:2009 case MVE_VST40_32_wb:2010 case MVE_VST41_32:2011 case MVE_VST41_32_wb:2012 case MVE_VST42_32:2013 case MVE_VST42_32_wb:2014 case MVE_VST43_32:2015 case MVE_VST43_32_wb:2016 case MVE_VSTRB32:2017 case MVE_VSTRB32_post:2018 case MVE_VSTRB32_pre:2019 case MVE_VSTRB32_rq:2020 case MVE_VSTRH32:2021 case MVE_VSTRH32_post:2022 case MVE_VSTRH32_pre:2023 case MVE_VSTRH32_rq:2024 case MVE_VSTRH32_rq_u:2025 case MVE_VSTRW32_qi:2026 case MVE_VSTRW32_qi_pre:2027 case MVE_VSTRW32_rq:2028 case MVE_VSTRW32_rq_u:2029 case MVE_VSTRWU32:2030 case MVE_VSTRWU32_post:2031 case MVE_VSTRWU32_pre:2032 case MVE_VSUB_qr_f32:2033 case MVE_VSUB_qr_i32:2034 case MVE_VSUBf32:2035 case MVE_VSUBi32:2036 return 2;2037 case MVE_VCTP64:2038 case MVE_VLDRDU64_qi:2039 case MVE_VLDRDU64_qi_pre:2040 case MVE_VLDRDU64_rq:2041 case MVE_VLDRDU64_rq_u:2042 case MVE_VMULLBs32:2043 case MVE_VMULLBu32:2044 case MVE_VMULLTs32:2045 case MVE_VMULLTu32:2046 case MVE_VMOVimmi64:2047 case MVE_VREV64_16:2048 case MVE_VREV64_32:2049 case MVE_VREV64_8:2050 case MVE_VSTRD64_qi:2051 case MVE_VSTRD64_qi_pre:2052 case MVE_VSTRD64_rq:2053 case MVE_VSTRD64_rq_u:2054 return 3;2055 }2056 };2057 LLVMInitializeARMTargetInfo();2058 LLVMInitializeARMTarget();2059 LLVMInitializeARMTargetMC();2060 2061 Triple TT("thumbv8.1m.main-none-none-eabi");2062 std::string Error;2063 const Target *T = TargetRegistry::lookupTarget(TT, Error);2064 if (!T) {2065 dbgs() << Error;2066 GTEST_SKIP();2067 }2068 2069 TargetOptions Options;2070 auto TM = std::unique_ptr<TargetMachine>(2071 T->createTargetMachine(TT, "generic", "", Options, std::nullopt,2072 std::nullopt, CodeGenOptLevel::Default));2073 ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),2074 std::string(TM->getTargetFeatureString()),2075 *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);2076 2077 auto MII = TM->getMCInstrInfo();2078 for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {2079 uint64_t Flags = MII->get(i).TSFlags;2080 if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)2081 continue;2082 int Size = (Flags & ARMII::VecSize) >> ARMII::VecSizeShift;2083 ASSERT_EQ(MVEVecSize(i), Size)2084 << MII->getName(i)2085 << ": mismatched expectation for MVE vec size\n";2086 }2087}2088