131 lines · cpp
1//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "Target.h"10 11#include <cassert>12 13#include "MCTargetDesc/MipsMCTargetDesc.h"14#include "TestBase.h"15#include "llvm/MC/TargetRegistry.h"16#include "llvm/Support/TargetSelect.h"17#include "gmock/gmock.h"18#include "gtest/gtest.h"19 20namespace llvm {21namespace exegesis {22namespace {23 24using testing::AllOf;25using testing::ElementsAre;26using testing::Eq;27using testing::Matcher;28using testing::Property;29 30Matcher<MCOperand> IsImm(int64_t Value) {31 return AllOf(Property(&MCOperand::isImm, Eq(true)),32 Property(&MCOperand::getImm, Eq(Value)));33}34 35Matcher<MCOperand> IsReg(unsigned Reg) {36 return AllOf(Property(&MCOperand::isReg, Eq(true)),37 Property(&MCOperand::getReg, Eq(Reg)));38}39 40Matcher<MCInst> OpcodeIs(unsigned Opcode) {41 return Property(&MCInst::getOpcode, Eq(Opcode));42}43 44Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {45 const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64;46 const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64;47 return AllOf(OpcodeIs(ORi),48 ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value)));49}50 51Matcher<MCInst> IsLoadHigh16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {52 const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64;53 return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value)));54}55 56Matcher<MCInst> IsShift(unsigned Reg, uint16_t Amount, bool IsGPR32) {57 const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64;58 return AllOf(OpcodeIs(SLL),59 ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount)));60}61 62class MipsTargetTest : public MipsTestBase {63protected:64 std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {65 return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,66 Value);67 }68};69 70TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) {71 const uint16_t Value = 0xFFFFU;72 const unsigned Reg = Mips::T0;73 EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),74 ElementsAre(IsLoadLow16BitImm(Reg, Value, true)));75}76 77TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) {78 const uint16_t Value = 0xFFFFU;79 const unsigned Reg = Mips::T0_64;80 EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),81 ElementsAre(IsLoadLow16BitImm(Reg, Value, false)));82}83 84TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {85 const uint32_t Value0 = 0xFFFF0000UL;86 const unsigned Reg0 = Mips::T0;87 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),88 ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true)));89 const uint32_t Value1 = 0xFFFFFFFFUL;90 const unsigned Reg1 = Mips::T1;91 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),92 ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true),93 IsLoadLow16BitImm(Reg1, 0xFFFFU, true)));94}95 96TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) {97 const uint32_t Value0 = 0x7FFF0000UL;98 const unsigned Reg0 = Mips::T0_64;99 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),100 ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false)));101 const uint32_t Value1 = 0x7FFFFFFFUL;102 const unsigned Reg1 = Mips::T1_64;103 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),104 ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false),105 IsLoadLow16BitImm(Reg1, 0xFFFFU, false)));106 const uint32_t Value2 = 0xFFFF0000UL;107 const unsigned Reg2 = Mips::T2_64;108 EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)),109 ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false),110 IsShift(Reg2, 16, false)));111 const uint32_t Value3 = 0xFFFFFFFFUL;112 const unsigned Reg3 = Mips::T3_64;113 EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)),114 ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false),115 IsShift(Reg3, 16, false),116 IsLoadLow16BitImm(Reg3, 0xFFFFU, false)));117}118 119TEST_F(MipsTargetTest, DefaultPfmCounters) {120 const std::string Expected = "CYCLES";121 EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,122 Expected);123 EXPECT_EQ(124 State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,125 Expected);126}127 128} // namespace129} // namespace exegesis130} // namespace llvm131