123 lines · cpp
1//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "../Common/AssemblerUtils.h"10#include "LlvmState.h"11#include "MCInstrDescView.h"12#include "ParallelSnippetGenerator.h"13#include "RISCVInstrInfo.h"14#include "RegisterAliasing.h"15#include "SerialSnippetGenerator.h"16#include "TestBase.h"17 18namespace llvm {19namespace exegesis {20namespace {21 22using testing::AnyOf;23using testing::ElementsAre;24using testing::HasSubstr;25using testing::SizeIs;26 27MATCHER(IsInvalid, "") { return !arg.isValid(); }28MATCHER(IsReg, "") { return arg.isReg(); }29 30template <typename SnippetGeneratorT>31class RISCVSnippetGeneratorTest : public RISCVTestBase {32protected:33 RISCVSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}34 35 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {36 randomGenerator().seed(0); // Initialize seed.37 const Instruction &Instr = State.getIC().getInstr(Opcode);38 auto CodeTemplateOrError = Generator.generateCodeTemplates(39 &Instr, State.getRATC().emptyRegisters());40 EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.41 return std::move(CodeTemplateOrError.get());42 }43 44 SnippetGeneratorT Generator;45};46 47using RISCVSerialSnippetGeneratorTest =48 RISCVSnippetGeneratorTest<SerialSnippetGenerator>;49 50using RISCVParallelSnippetGeneratorTest =51 RISCVSnippetGeneratorTest<ParallelSnippetGenerator>;52 53TEST_F(RISCVSerialSnippetGeneratorTest,54 ImplicitSelfDependencyThroughExplicitRegs) {55 // - ADD56 // - Op0 Explicit Def RegClass(GPR)57 // - Op1 Explicit Use RegClass(GPR)58 // - Op2 Explicit Use RegClass(GPR)59 // - Var0 [Op0]60 // - Var1 [Op1]61 // - Var2 [Op2]62 // - hasAliasingRegisters63 const unsigned Opcode = RISCV::ADD;64 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);65 ASSERT_THAT(CodeTemplates, SizeIs(1));66 const auto &CT = CodeTemplates[0];67 EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);68 ASSERT_THAT(CT.Instructions, SizeIs(1));69 const InstructionTemplate &IT = CT.Instructions[0];70 EXPECT_THAT(IT.getOpcode(), Opcode);71 ASSERT_THAT(IT.getVariableValues(), SizeIs(3));72 EXPECT_THAT(IT.getVariableValues(),73 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),74 ElementsAre(IsReg(), IsReg(), IsInvalid())))75 << "Op0 is either set to Op1 or to Op2";76}77 78TEST_F(RISCVSerialSnippetGeneratorTest,79 ImplicitSelfDependencyThroughExplicitRegsForbidAll) {80 // - XOR81 // - Op0 Explicit Def RegClass(GPR)82 // - Op1 Explicit Use RegClass(GPR)83 // - Op2 Explicit Use RegClass(GPR)84 // - Var0 [Op0]85 // - Var1 [Op1]86 // - Var2 [Op2]87 // - hasAliasingRegisters88 randomGenerator().seed(0); // Initialize seed.89 const Instruction &Instr = State.getIC().getInstr(RISCV::XOR);90 auto AllRegisters = State.getRATC().emptyRegisters();91 AllRegisters.flip();92 EXPECT_TRUE(errorToBool(93 Generator.generateCodeTemplates(&Instr, AllRegisters).takeError()));94}95 96TEST_F(RISCVParallelSnippetGeneratorTest, MemoryUse) {97 // LB reads from memory.98 // - LB99 // - Op0 Explicit Def RegClass(GPR)100 // - Op1 Explicit Use Memory RegClass(GPR)101 // - Op2 Explicit Use Memory102 // - Var0 [Op0]103 // - Var1 [Op1]104 // - Var2 [Op2]105 // - hasMemoryOperands106 const unsigned Opcode = RISCV::LB;107 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);108 ASSERT_THAT(CodeTemplates, SizeIs(1));109 const auto &CT = CodeTemplates[0];110 EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables"));111 EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);112 ASSERT_THAT(CT.Instructions,113 SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));114 const InstructionTemplate &IT = CT.Instructions[0];115 EXPECT_THAT(IT.getOpcode(), Opcode);116 ASSERT_THAT(IT.getVariableValues(), SizeIs(3));117 EXPECT_EQ(IT.getVariableValues()[1].getReg(), RISCV::X10);118}119 120} // namespace121} // namespace exegesis122} // namespace llvm123