98 lines · cpp
1//===-- SchedClassResolutionTest.cpp ----------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "SchedClassResolution.h"10 11#include <cassert>12 13#include "TestBase.h"14#include "llvm/MC/TargetRegistry.h"15#include "llvm/Support/TargetSelect.h"16#include "gmock/gmock.h"17#include "gtest/gtest.h"18 19namespace llvm {20namespace exegesis {21namespace {22 23using testing::Pair;24using testing::UnorderedElementsAre;25 26class X86SchedClassResolutionTest : public X86TestBase {27protected:28 X86SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {29 // Compute the ProxResIdx of ports uses in tests.30 const auto &SM = STI.getSchedModel();31 for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {32 const std::string Name = SM.getProcResource(I)->Name;33 if (Name == "HWPort0") {34 P0Idx = I;35 } else if (Name == "HWPort1") {36 P1Idx = I;37 } else if (Name == "HWPort5") {38 P5Idx = I;39 } else if (Name == "HWPort6") {40 P6Idx = I;41 } else if (Name == "HWPort05") {42 P05Idx = I;43 } else if (Name == "HWPort0156") {44 P0156Idx = I;45 }46 }47 EXPECT_NE(P0Idx, 0);48 EXPECT_NE(P1Idx, 0);49 EXPECT_NE(P5Idx, 0);50 EXPECT_NE(P6Idx, 0);51 EXPECT_NE(P05Idx, 0);52 EXPECT_NE(P0156Idx, 0);53 }54 55protected:56 const MCSubtargetInfo &STI;57 uint16_t P0Idx = 0;58 uint16_t P1Idx = 0;59 uint16_t P5Idx = 0;60 uint16_t P6Idx = 0;61 uint16_t P05Idx = 0;62 uint16_t P0156Idx = 0;63};64 65TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {66 const auto Pressure =67 computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2, 0}});68 EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));69}70 71TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {72 const auto Pressure =73 computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2, 0}});74 EXPECT_THAT(Pressure,75 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));76}77 78TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {79 const auto Pressure = computeIdealizedProcResPressure(80 STI.getSchedModel(), {{P05Idx, 2, 0}, {P0156Idx, 2, 0}});81 EXPECT_THAT(Pressure,82 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),83 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));84}85 86TEST_F(X86SchedClassResolutionTest,87 ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {88 const auto Pressure = computeIdealizedProcResPressure(89 STI.getSchedModel(), {{P1Idx, 1, 0}, {P05Idx, 1, 0}, {P0156Idx, 2, 0}});90 EXPECT_THAT(Pressure,91 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),92 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));93}94 95} // namespace96} // namespace exegesis97} // namespace llvm98