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1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This tablegen backend emits a target specifier matcher for converting parsed10// assembly operands in the MCInst structures. It also emits a matcher for11// custom operand parsing.12//13// Converting assembly operands into MCInst structures14// ---------------------------------------------------15//16// The input to the target specific matcher is a list of literal tokens and17// operands. The target specific parser should generally eliminate any syntax18// which is not relevant for matching; for example, comma tokens should have19// already been consumed and eliminated by the parser. Most instructions will20// end up with a single literal token (the instruction name) and some number of21// operands.22//23// Some example inputs, for X86:24//   'addl' (immediate ...) (register ...)25//   'add' (immediate ...) (memory ...)26//   'call' '*' %epc27//28// The assembly matcher is responsible for converting this input into a precise29// machine instruction (i.e., an instruction with a well defined encoding). This30// mapping has several properties which complicate matching:31//32//  - It may be ambiguous; many architectures can legally encode particular33//    variants of an instruction in different ways (for example, using a smaller34//    encoding for small immediates). Such ambiguities should never be35//    arbitrarily resolved by the assembler, the assembler is always responsible36//    for choosing the "best" available instruction.37//38//  - It may depend on the subtarget or the assembler context. Instructions39//    which are invalid for the current mode, but otherwise unambiguous (e.g.,40//    an SSE instruction in a file being assembled for i486) should be accepted41//    and rejected by the assembler front end. However, if the proper encoding42//    for an instruction is dependent on the assembler context then the matcher43//    is responsible for selecting the correct machine instruction for the44//    current mode.45//46// The core matching algorithm attempts to exploit the regularity in most47// instruction sets to quickly determine the set of possibly matching48// instructions, and the simplify the generated code. Additionally, this helps49// to ensure that the ambiguities are intentionally resolved by the user.50//51// The matching is divided into two distinct phases:52//53//   1. Classification: Each operand is mapped to the unique set which (a)54//      contains it, and (b) is the largest such subset for which a single55//      instruction could match all members.56//57//      For register classes, we can generate these subgroups automatically. For58//      arbitrary operands, we expect the user to define the classes and their59//      relations to one another (for example, 8-bit signed immediates as a60//      subset of 32-bit immediates).61//62//      By partitioning the operands in this way, we guarantee that for any63//      tuple of classes, any single instruction must match either all or none64//      of the sets of operands which could classify to that tuple.65//66//      In addition, the subset relation amongst classes induces a partial order67//      on such tuples, which we use to resolve ambiguities.68//69//   2. The input can now be treated as a tuple of classes (static tokens are70//      simple singleton sets). Each such tuple should generally map to a single71//      instruction (we currently ignore cases where this isn't true, whee!!!),72//      which we can emit a simple matcher for.73//74// Custom Operand Parsing75// ----------------------76//77//  Some targets need a custom way to parse operands, some specific instructions78//  can contain arguments that can represent processor flags and other kinds of79//  identifiers that need to be mapped to specific values in the final encoded80//  instructions. The target specific custom operand parsing works in the81//  following way:82//83//   1. A operand match table is built, each entry contains a mnemonic, an84//      operand class, a mask for all operand positions for that same85//      class/mnemonic and target features to be checked while trying to match.86//87//   2. The operand matcher will try every possible entry with the same88//      mnemonic and will check if the target feature for this mnemonic also89//      matches. After that, if the operand to be matched has its index90//      present in the mask, a successful match occurs. Otherwise, fallback91//      to the regular operand parsing.92//93//   3. For a match success, each operand class that has a 'ParserMethod'94//      becomes part of a switch from where the custom method is called.95//96//===----------------------------------------------------------------------===//97 98#include "Common/CodeGenInstAlias.h"99#include "Common/CodeGenInstruction.h"100#include "Common/CodeGenRegisters.h"101#include "Common/CodeGenTarget.h"102#include "Common/SubtargetFeatureInfo.h"103#include "Common/Types.h"104#include "llvm/ADT/CachedHashString.h"105#include "llvm/ADT/PointerUnion.h"106#include "llvm/ADT/STLExtras.h"107#include "llvm/ADT/SmallPtrSet.h"108#include "llvm/ADT/SmallVector.h"109#include "llvm/ADT/StringExtras.h"110#include "llvm/Support/CommandLine.h"111#include "llvm/Support/Debug.h"112#include "llvm/Support/ErrorHandling.h"113#include "llvm/Support/FormatVariadic.h"114#include "llvm/TableGen/Error.h"115#include "llvm/TableGen/Record.h"116#include "llvm/TableGen/StringMatcher.h"117#include "llvm/TableGen/StringToOffsetTable.h"118#include "llvm/TableGen/TableGenBackend.h"119#include <cassert>120#include <cctype>121#include <forward_list>122#include <map>123#include <set>124 125using namespace llvm;126 127#define DEBUG_TYPE "asm-matcher-emitter"128 129static cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");130 131static cl::opt<std::string>132    MatchPrefix("match-prefix", cl::init(""),133                cl::desc("Only match instructions with the given prefix"),134                cl::cat(AsmMatcherEmitterCat));135 136namespace {137class AsmMatcherInfo;138 139// Register sets are used as keys in some second-order sets TableGen creates140// when generating its data structures. This means that the order of two141// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and142// can even affect compiler output (at least seen in diagnostics produced when143// all matches fail). So we use a type that sorts them consistently.144using RegisterSet = std::set<const Record *, LessRecordByID>;145 146class AsmMatcherEmitter {147  const RecordKeeper &Records;148 149public:150  AsmMatcherEmitter(const RecordKeeper &R) : Records(R) {}151 152  void run(raw_ostream &o);153};154 155/// ClassInfo - Helper class for storing the information about a particular156/// class of operands which can be matched.157struct ClassInfo {158  enum ClassInfoKind {159    /// Invalid kind, for use as a sentinel value.160    Invalid = 0,161 162    /// The class for a particular token.163    Token,164 165    /// The (first) register class, subsequent register classes are166    /// RegisterClass0+1, and so on.167    RegisterClass0,168 169    /// The (first) register class by hwmode, subsequent register classes by170    /// hwmode are RegisterClassByHwMode0+1, and so on.171    RegisterClassByHwMode0 = 1 << 12,172 173    /// The (first) user defined class, subsequent user defined classes are174    /// UserClass0+1, and so on.175    UserClass0 = 1 << 24176  };177 178  /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +179  /// N) for the Nth user defined class.180  unsigned Kind = 0;181 182  /// SuperClasses - The super classes of this class. Note that for simplicities183  /// sake user operands only record their immediate super class, while register184  /// operands include all superclasses.185  std::vector<ClassInfo *> SuperClasses;186 187  /// Name - The full class name, suitable for use in an enum.188  std::string Name;189 190  /// ClassName - The unadorned generic name for this class (e.g., Token).191  std::string ClassName;192 193  /// ValueName - The name of the value this class represents; for a token this194  /// is the literal token string, for an operand it is the TableGen class (or195  /// empty if this is a derived class).196  std::string ValueName;197 198  /// PredicateMethod - The name of the operand method to test whether the199  /// operand matches this class; this is not valid for Token or register kinds.200  std::string PredicateMethod;201 202  /// RenderMethod - The name of the operand method to add this operand to an203  /// MCInst; this is not valid for Token or register kinds.204  std::string RenderMethod;205 206  /// ParserMethod - The name of the operand method to do a target specific207  /// parsing on the operand.208  std::string ParserMethod;209 210  /// For register classes: the records for all the registers in this class.211  RegisterSet Registers;212 213  /// For custom match classes: the diagnostic kind for when the predicate214  /// fails.215  std::string DiagnosticType;216 217  /// For custom match classes: the diagnostic string for when the predicate218  /// fails.219  std::string DiagnosticString;220 221  /// Is this operand optional and not always required.222  bool IsOptional = false;223 224  /// DefaultMethod - The name of the method that returns the default operand225  /// for optional operand226  std::string DefaultMethod;227 228public:229  /// isRegisterClass() - Check if this is a register class.230  bool isRegisterClass() const {231    return Kind >= RegisterClass0 && Kind < RegisterClassByHwMode0;232  }233 234  bool isRegisterClassByHwMode() const {235    return Kind >= RegisterClassByHwMode0 && Kind < UserClass0;236  }237 238  /// isUserClass() - Check if this is a user defined class.239  bool isUserClass() const { return Kind >= UserClass0; }240 241  /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes242  /// are related if they are in the same class hierarchy.243  bool isRelatedTo(const ClassInfo &RHS) const {244    // Tokens are only related to tokens.245    if (Kind == Token || RHS.Kind == Token)246      return Kind == Token && RHS.Kind == Token;247 248    // Registers classes are only related to registers classes, and only if249    // their intersection is non-empty.250    if (isRegisterClass() || RHS.isRegisterClass()) {251      if (!isRegisterClass() || !RHS.isRegisterClass())252        return false;253 254      std::vector<const Record *> Tmp;255      std::set_intersection(Registers.begin(), Registers.end(),256                            RHS.Registers.begin(), RHS.Registers.end(),257                            std::back_inserter(Tmp), LessRecordByID());258 259      return !Tmp.empty();260    }261 262    if (isRegisterClassByHwMode() || RHS.isRegisterClassByHwMode())263      return isRegisterClassByHwMode() == RHS.isRegisterClassByHwMode();264 265    // Otherwise we have two users operands; they are related if they are in the266    // same class hierarchy.267    //268    // FIXME: This is an oversimplification, they should only be related if they269    // intersect, however we don't have that information.270    assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");271    const ClassInfo *Root = this;272    while (!Root->SuperClasses.empty())273      Root = Root->SuperClasses.front();274 275    const ClassInfo *RHSRoot = &RHS;276    while (!RHSRoot->SuperClasses.empty())277      RHSRoot = RHSRoot->SuperClasses.front();278 279    return Root == RHSRoot;280  }281 282  /// isSubsetOf - Test whether this class is a subset of \p RHS.283  bool isSubsetOf(const ClassInfo &RHS) const {284    // This is a subset of RHS if it is the same class...285    if (this == &RHS)286      return true;287 288    // ... or if any of its super classes are a subset of RHS.289    SmallVector<const ClassInfo *, 16> Worklist(SuperClasses.begin(),290                                                SuperClasses.end());291    SmallPtrSet<const ClassInfo *, 16> Visited;292    while (!Worklist.empty()) {293      auto *CI = Worklist.pop_back_val();294      if (CI == &RHS)295        return true;296      for (auto *Super : CI->SuperClasses)297        if (Visited.insert(Super).second)298          Worklist.push_back(Super);299    }300 301    return false;302  }303 304  int getTreeDepth() const {305    int Depth = 0;306    const ClassInfo *Root = this;307    while (!Root->SuperClasses.empty()) {308      Depth++;309      Root = Root->SuperClasses.front();310    }311    return Depth;312  }313 314  const ClassInfo *findRoot() const {315    const ClassInfo *Root = this;316    while (!Root->SuperClasses.empty())317      Root = Root->SuperClasses.front();318    return Root;319  }320 321  /// Compare two classes. This does not produce a total ordering, but does322  /// guarantee that subclasses are sorted before their parents, and that the323  /// ordering is transitive.324  bool operator<(const ClassInfo &RHS) const {325    if (this == &RHS)326      return false;327 328    // First, enforce the ordering between the three different types of class.329    // Tokens sort before registers, which sort before regclass by hwmode, which330    // sort before user classes.331    if (Kind == Token) {332      if (RHS.Kind != Token)333        return true;334      assert(RHS.Kind == Token);335    } else if (isRegisterClass()) {336      if (RHS.Kind == Token)337        return false;338      else if (RHS.isUserClass() || RHS.isRegisterClassByHwMode())339        return true;340      assert(RHS.isRegisterClass());341    } else if (isRegisterClassByHwMode()) {342      if (RHS.Kind == Token || RHS.isRegisterClass())343        return false;344      else if (RHS.isUserClass())345        return true;346      assert(RHS.isRegisterClassByHwMode());347    } else if (isUserClass()) {348      if (!RHS.isUserClass())349        return false;350      assert(RHS.isUserClass());351    } else {352      llvm_unreachable("Unknown ClassInfoKind");353    }354 355    if (Kind == Token || isUserClass()) {356      // Related tokens and user classes get sorted by depth in the inheritence357      // tree (so that subclasses are before their parents).358      if (isRelatedTo(RHS)) {359        if (getTreeDepth() > RHS.getTreeDepth())360          return true;361        if (getTreeDepth() < RHS.getTreeDepth())362          return false;363      } else {364        // Unrelated tokens and user classes are ordered by the name of their365        // root nodes, so that there is a consistent ordering between366        // unconnected trees.367        return findRoot()->ValueName < RHS.findRoot()->ValueName;368      }369    } else if (isRegisterClass()) {370      // For register sets, sort by number of registers. This guarantees that371      // a set will always sort before all of it's strict supersets.372      if (Registers.size() != RHS.Registers.size())373        return Registers.size() < RHS.Registers.size();374    } else if (isRegisterClassByHwMode()) {375      // Ensure the MCK enum entries are in the same order as RegClassIDs. The376      // lookup table to from RegByHwMode to concrete class relies on it.377      return Kind < RHS.Kind;378    } else {379      llvm_unreachable("Unknown ClassInfoKind");380    }381 382    // FIXME: We should be able to just return false here, as we only need a383    // partial order (we use stable sorts, so this is deterministic) and the384    // name of a class shouldn't be significant. However, some of the backends385    // accidentally rely on this behaviour, so it will have to stay like this386    // until they are fixed.387    return ValueName < RHS.ValueName;388  }389};390 391class AsmVariantInfo {392public:393  StringRef RegisterPrefix;394  StringRef TokenizingCharacters;395  StringRef SeparatorCharacters;396  StringRef BreakCharacters;397  StringRef Name;398  int AsmVariantNo;399};400 401bool getPreferSmallerInstructions(CodeGenTarget const &Target) {402  return Target.getAsmParser()->getValueAsBit("PreferSmallerInstructions");403}404 405/// MatchableInfo - Helper class for storing the necessary information for an406/// instruction or alias which is capable of being matched.407struct MatchableInfo {408  struct AsmOperand {409    /// Token - This is the token that the operand came from.410    StringRef Token;411 412    /// The unique class instance this operand should match.413    ClassInfo *Class = nullptr;414 415    /// The operand name this is, if anything.416    StringRef SrcOpName;417 418    /// The operand name this is, before renaming for tied operands.419    StringRef OrigSrcOpName;420 421    /// The suboperand index within SrcOpName, or -1 for the entire operand.422    int SubOpIdx = -1;423 424    /// Whether the token is "isolated", i.e., it is preceded and followed425    /// by separators.426    bool IsIsolatedToken;427 428    /// Register record if this token is singleton register.429    const Record *SingletonReg = nullptr;430 431    explicit AsmOperand(bool IsIsolatedToken, StringRef T)432        : Token(T), IsIsolatedToken(IsIsolatedToken) {}433  };434 435  /// ResOperand - This represents a single operand in the result instruction436  /// generated by the match.  In cases (like addressing modes) where a single437  /// assembler operand expands to multiple MCOperands, this represents the438  /// single assembler operand, not the MCOperand.439  struct ResOperand {440    enum {441      /// RenderAsmOperand - This represents an operand result that is442      /// generated by calling the render method on the assembly operand.  The443      /// corresponding AsmOperand is specified by AsmOperandNum.444      RenderAsmOperand,445 446      /// TiedOperand - This represents a result operand that is a duplicate of447      /// a previous result operand.448      TiedOperand,449 450      /// ImmOperand - This represents an immediate value that is dumped into451      /// the operand.452      ImmOperand,453 454      /// RegOperand - This represents a fixed register that is dumped in.455      RegOperand456    } Kind;457 458    /// Tuple containing the index of the (earlier) result operand that should459    /// be copied from, as well as the indices of the corresponding (parsed)460    /// operands in the asm string.461    struct TiedOperandsTuple {462      unsigned ResOpnd;463      unsigned SrcOpnd1Idx;464      unsigned SrcOpnd2Idx;465    };466 467    union {468      /// This is the operand # in the AsmOperands list that this should be469      /// copied from.470      unsigned AsmOperandNum;471 472      /// Description of tied operands.473      TiedOperandsTuple TiedOperands;474 475      /// ImmVal - This is the immediate value added to the instruction.476      int64_t ImmVal;477 478      /// Register - This is the register record.479      const Record *Register;480    };481 482    /// MINumOperands - The number of MCInst operands populated by this483    /// operand.484    unsigned MINumOperands;485 486    static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {487      ResOperand X;488      X.Kind = RenderAsmOperand;489      X.AsmOperandNum = AsmOpNum;490      X.MINumOperands = NumOperands;491      return X;492    }493 494    static ResOperand getTiedOp(unsigned TiedOperandNum, unsigned SrcOperand1,495                                unsigned SrcOperand2) {496      ResOperand X;497      X.Kind = TiedOperand;498      X.TiedOperands = {TiedOperandNum, SrcOperand1, SrcOperand2};499      X.MINumOperands = 1;500      return X;501    }502 503    static ResOperand getImmOp(int64_t Val) {504      ResOperand X;505      X.Kind = ImmOperand;506      X.ImmVal = Val;507      X.MINumOperands = 1;508      return X;509    }510 511    static ResOperand getRegOp(const Record *Reg) {512      ResOperand X;513      X.Kind = RegOperand;514      X.Register = Reg;515      X.MINumOperands = 1;516      return X;517    }518  };519 520  /// AsmVariantID - Target's assembly syntax variant no.521  int AsmVariantID;522 523  /// AsmString - The assembly string for this instruction (with variants524  /// removed), e.g. "movsx $src, $dst".525  std::string AsmString;526 527  /// TheDef - This is the definition of the instruction or InstAlias that this528  /// matchable came from.529  const Record *const TheDef;530 531  // ResInstSize - The size of the resulting instruction for this matchable.532  unsigned ResInstSize;533 534  /// DefRec - This is the definition that it came from.535  PointerUnion<const CodeGenInstruction *, const CodeGenInstAlias *> DefRec;536 537  const CodeGenInstruction *getResultInst() const {538    if (isa<const CodeGenInstruction *>(DefRec))539      return cast<const CodeGenInstruction *>(DefRec);540    return cast<const CodeGenInstAlias *>(DefRec)->ResultInst;541  }542 543  /// ResOperands - This is the operand list that should be built for the result544  /// MCInst.545  SmallVector<ResOperand, 8> ResOperands;546 547  /// Mnemonic - This is the first token of the matched instruction, its548  /// mnemonic.549  StringRef Mnemonic;550 551  /// AsmOperands - The textual operands that this instruction matches,552  /// annotated with a class and where in the OperandList they were defined.553  /// This directly corresponds to the tokenized AsmString after the mnemonic is554  /// removed.555  SmallVector<AsmOperand, 8> AsmOperands;556 557  /// Predicates - The required subtarget features to match this instruction.558  SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;559 560  /// ConversionFnKind - The enum value which is passed to the generated561  /// convertToMCInst to convert parsed operands into an MCInst for this562  /// function.563  std::string ConversionFnKind;564 565  /// If this instruction is deprecated in some form.566  bool HasDeprecation = false;567 568  /// If this is an alias, this is use to determine whether or not to using569  /// the conversion function defined by the instruction's AsmMatchConverter570  /// or to use the function generated by the alias.571  bool UseInstAsmMatchConverter;572 573  MatchableInfo(const CodeGenInstruction &CGI)574      : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef),575        ResInstSize(TheDef->getValueAsInt("Size")), DefRec(&CGI),576        UseInstAsmMatchConverter(true) {}577 578  MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)579      : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),580        ResInstSize(Alias->ResultInst->TheDef->getValueAsInt("Size")),581        DefRec(Alias.release()), UseInstAsmMatchConverter(TheDef->getValueAsBit(582                                     "UseInstAsmMatchConverter")) {}583 584  // Could remove this and the dtor if PointerUnion supported unique_ptr585  // elements with a dynamic failure/assertion (like the one below) in the case586  // where it was copied while being in an owning state.587  MatchableInfo(const MatchableInfo &RHS)588      : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),589        TheDef(RHS.TheDef), ResInstSize(RHS.ResInstSize), DefRec(RHS.DefRec),590        ResOperands(RHS.ResOperands), Mnemonic(RHS.Mnemonic),591        AsmOperands(RHS.AsmOperands), RequiredFeatures(RHS.RequiredFeatures),592        ConversionFnKind(RHS.ConversionFnKind),593        HasDeprecation(RHS.HasDeprecation),594        UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {595    assert(!isa<const CodeGenInstAlias *>(DefRec));596  }597 598  ~MatchableInfo() {599    delete dyn_cast_if_present<const CodeGenInstAlias *>(DefRec);600  }601 602  // Two-operand aliases clone from the main matchable, but mark the second603  // operand as a tied operand of the first for purposes of the assembler.604  void formTwoOperandAlias(StringRef Constraint);605 606  void initialize(const AsmMatcherInfo &Info,607                  SmallPtrSetImpl<const Record *> &SingletonRegisters,608                  AsmVariantInfo const &Variant, bool HasMnemonicFirst);609 610  /// validate - Return true if this matchable is a valid thing to match against611  /// and perform a bunch of validity checking.612  bool validate(StringRef CommentDelimiter, bool IsAlias) const;613 614  /// findAsmOperand - Find the AsmOperand with the specified name and615  /// suboperand index.616  int findAsmOperand(StringRef N, int SubOpIdx) const {617    auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {618      return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;619    });620    return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;621  }622 623  /// findAsmOperandNamed - Find the first AsmOperand with the specified name.624  /// This does not check the suboperand index.625  int findAsmOperandNamed(StringRef N, int LastIdx = -1) const {626    auto I =627        llvm::find_if(llvm::drop_begin(AsmOperands, LastIdx + 1),628                      [&](const AsmOperand &Op) { return Op.SrcOpName == N; });629    return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;630  }631 632  int findAsmOperandOriginallyNamed(StringRef N) const {633    auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {634      return Op.OrigSrcOpName == N;635    });636    return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;637  }638 639  void buildInstructionResultOperands();640  void buildAliasResultOperands(bool AliasConstraintsAreChecked);641 642  /// shouldBeMatchedBefore - Compare two matchables for ordering.643  bool shouldBeMatchedBefore(const MatchableInfo &RHS,644                             bool PreferSmallerInstructions) const {645    // The primary comparator is the instruction mnemonic.646    if (int Cmp = Mnemonic.compare_insensitive(RHS.Mnemonic))647      return Cmp == -1;648 649    // (Optionally) Order by the resultant instuctions size.650    // eg. for ARM thumb instructions smaller encodings should be preferred.651    if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)652      return ResInstSize < RHS.ResInstSize;653 654    if (AsmOperands.size() != RHS.AsmOperands.size())655      return AsmOperands.size() < RHS.AsmOperands.size();656 657    // Compare lexicographically by operand. The matcher validates that other658    // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().659    for (const auto &[LHSOp, RHSOp] : zip_equal(AsmOperands, RHS.AsmOperands)) {660      if (*LHSOp.Class < *RHSOp.Class)661        return true;662      if (*RHSOp.Class < *LHSOp.Class)663        return false;664    }665 666    // For X86 AVX/AVX512 instructions, we prefer vex encoding because the667    // vex encoding size is smaller. Since X86InstrSSE.td is included ahead668    // of X86InstrAVX512.td, the AVX instruction ID is less than AVX512 ID.669    // We use the ID to sort AVX instruction before AVX512 instruction in670    // matching table. As well as InstAlias.671    if (getResultInst()->TheDef->isSubClassOf("Instruction") &&672        getResultInst()->TheDef->getValueAsBit("HasPositionOrder") &&673        RHS.getResultInst()->TheDef->isSubClassOf("Instruction") &&674        RHS.getResultInst()->TheDef->getValueAsBit("HasPositionOrder"))675      return getResultInst()->TheDef->getID() <676             RHS.getResultInst()->TheDef->getID();677 678    // Give matches that require more features higher precedence. This is useful679    // because we cannot define AssemblerPredicates with the negation of680    // processor features. For example, ARM v6 "nop" may be either a HINT or681    // MOV. With v6, we want to match HINT. The assembler has no way to682    // predicate MOV under "NoV6", but HINT will always match first because it683    // requires V6 while MOV does not.684    if (RequiredFeatures.size() != RHS.RequiredFeatures.size())685      return RequiredFeatures.size() > RHS.RequiredFeatures.size();686 687    return false;688  }689 690  /// couldMatchAmbiguouslyWith - Check whether this matchable could691  /// ambiguously match the same set of operands as \p RHS (without being a692  /// strictly superior match).693  bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS,694                                 bool PreferSmallerInstructions) const {695    // The primary comparator is the instruction mnemonic.696    if (Mnemonic != RHS.Mnemonic)697      return false;698 699    // Different variants can't conflict.700    if (AsmVariantID != RHS.AsmVariantID)701      return false;702 703    // The size of instruction is unambiguous.704    if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)705      return false;706 707    // The number of operands is unambiguous.708    if (AsmOperands.size() != RHS.AsmOperands.size())709      return false;710 711    // Otherwise, make sure the ordering of the two instructions is unambiguous712    // by checking that either (a) a token or operand kind discriminates them,713    // or (b) the ordering among equivalent kinds is consistent.714 715    // Tokens and operand kinds are unambiguous (assuming a correct target716    // specific parser).717    for (const auto &[LHSOp, RHSOp] : zip_equal(AsmOperands, RHS.AsmOperands)) {718      if (LHSOp.Class->Kind != RHSOp.Class->Kind ||719          LHSOp.Class->Kind == ClassInfo::Token)720        if (*LHSOp.Class < *RHSOp.Class || *RHSOp.Class < *LHSOp.Class)721          return false;722    }723 724    // Otherwise, this operand could commute if all operands are equivalent, or725    // there is a pair of operands that compare less than and a pair that726    // compare greater than.727    bool HasLT = false, HasGT = false;728    for (const auto &[LHSOp, RHSOp] : zip_equal(AsmOperands, RHS.AsmOperands)) {729      if (*LHSOp.Class < *RHSOp.Class)730        HasLT = true;731      if (*RHSOp.Class < *LHSOp.Class)732        HasGT = true;733    }734 735    return HasLT == HasGT;736  }737 738  void dump() const;739 740private:741  void tokenizeAsmString(AsmMatcherInfo const &Info,742                         AsmVariantInfo const &Variant);743  void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);744};745 746struct OperandMatchEntry {747  unsigned OperandMask;748  const MatchableInfo *MI;749  ClassInfo *CI;750 751  static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,752                                  unsigned opMask) {753    OperandMatchEntry X;754    X.OperandMask = opMask;755    X.CI = ci;756    X.MI = mi;757    return X;758  }759};760 761class AsmMatcherInfo {762public:763  /// Tracked Records764  const RecordKeeper &Records;765 766  /// The tablegen AsmParser record.767  const Record *AsmParser;768 769  /// Target - The target information.770  const CodeGenTarget &Target;771 772  /// The classes which are needed for matching.773  std::forward_list<ClassInfo> Classes;774 775  /// The information on the matchables to match.776  std::vector<std::unique_ptr<MatchableInfo>> Matchables;777 778  /// Info for custom matching operands by user defined methods.779  std::vector<OperandMatchEntry> OperandMatchInfo;780 781  /// Map of Register records to their class information.782  using RegisterClassesTy =783      std::map<const Record *, ClassInfo *, LessRecordByID>;784  RegisterClassesTy RegisterClasses;785 786  /// Map of Predicate records to their subtarget information.787  SubtargetFeatureInfoMap SubtargetFeatures;788 789  /// Map of AsmOperandClass records to their class information.790  std::map<const Record *, ClassInfo *> AsmOperandClasses;791 792  /// Map of RegisterClass records to their class information.793  std::map<const Record *, ClassInfo *> RegisterClassClasses;794 795private:796  /// Map of token to class information which has already been constructed.797  std::map<std::string, ClassInfo *> TokenClasses;798 799private:800  /// getTokenClass - Lookup or create the class for the given token.801  ClassInfo *getTokenClass(StringRef Token);802 803  /// getOperandClass - Lookup or create the class for the given operand.804  ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,805                             int SubOpIdx);806  ClassInfo *getOperandClass(const Record *Rec, int SubOpIdx);807 808  /// buildRegisterClasses - Build the ClassInfo* instances for register809  /// classes.810  void811  buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters);812 813  /// buildOperandClasses - Build the ClassInfo* instances for user defined814  /// operand classes.815  void buildOperandClasses();816 817  void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,818                                        unsigned AsmOpIdx);819  void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,820                                  MatchableInfo::AsmOperand &Op);821 822public:823  AsmMatcherInfo(const Record *AsmParser, const CodeGenTarget &Target,824                 const RecordKeeper &Records);825 826  /// Construct the various tables used during matching.827  void buildInfo();828 829  /// buildOperandMatchInfo - Build the necessary information to handle user830  /// defined operand parsing methods.831  void buildOperandMatchInfo();832 833  /// getSubtargetFeature - Lookup or create the subtarget feature info for the834  /// given operand.835  const SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {836    assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");837    const auto &I = SubtargetFeatures.find(Def);838    return I == SubtargetFeatures.end() ? nullptr : &I->second;839  }840 841  const RecordKeeper &getRecords() const { return Records; }842 843  bool hasOptionalOperands() const {844    return any_of(Classes,845                  [](const ClassInfo &Class) { return Class.IsOptional; });846  }847};848 849} // end anonymous namespace850 851#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)852LLVM_DUMP_METHOD void MatchableInfo::dump() const {853  errs() << TheDef->getName() << " -- "854         << "flattened:\"" << AsmString << "\"\n";855 856  errs() << "  variant: " << AsmVariantID << "\n";857 858  for (const auto &[Idx, Op] : enumerate(AsmOperands)) {859    errs() << "  op[" << Idx << "] = " << Op.Class->ClassName << " - ";860    errs() << '\"' << Op.Token << "\"\n";861  }862}863#endif864 865static std::pair<StringRef, StringRef>866parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {867  // Trim whitespace and the leading '$' on the operand names.868  auto TrimWSDollar = [Loc](StringRef OpName) {869    OpName = OpName.trim(" \t");870    if (!OpName.consume_front("$"))871      PrintFatalError(Loc, "expected '$' prefix on asm operand name");872    return OpName;873  };874 875  // Split via the '='.876  auto [Src, Dst] = S.split('=');877  if (Dst == "")878    PrintFatalError(Loc, "missing '=' in two-operand alias constraint");879  return {TrimWSDollar(Src), TrimWSDollar(Dst)};880}881 882void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {883  // Figure out which operands are aliased and mark them as tied.884  auto [Src, Dst] = parseTwoOperandConstraint(Constraint, TheDef->getLoc());885 886  // Find the AsmOperands that refer to the operands we're aliasing.887  int SrcAsmOperand = findAsmOperandNamed(Src);888  int DstAsmOperand = findAsmOperandNamed(Dst);889  if (SrcAsmOperand == -1)890    PrintFatalError(TheDef->getLoc(),891                    "unknown source two-operand alias operand '" + Src + "'.");892  if (DstAsmOperand == -1)893    PrintFatalError(TheDef->getLoc(),894                    "unknown destination two-operand alias operand '" + Dst +895                        "'.");896 897  // Find the ResOperand that refers to the operand we're aliasing away898  // and update it to refer to the combined operand instead.899  for (ResOperand &Op : ResOperands) {900    if (Op.Kind == ResOperand::RenderAsmOperand &&901        Op.AsmOperandNum == (unsigned)SrcAsmOperand) {902      Op.AsmOperandNum = DstAsmOperand;903      break;904    }905  }906  // Remove the AsmOperand for the alias operand.907  AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);908  // Adjust the ResOperand references to any AsmOperands that followed909  // the one we just deleted.910  for (ResOperand &Op : ResOperands) {911    if (Op.Kind == ResOperand::RenderAsmOperand &&912        Op.AsmOperandNum > (unsigned)SrcAsmOperand)913      --Op.AsmOperandNum;914  }915}916 917/// extractSingletonRegisterForAsmOperand - Extract singleton register,918/// if present, from specified token.919static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,920                                                  const AsmMatcherInfo &Info,921                                                  StringRef RegisterPrefix) {922  StringRef Tok = Op.Token;923 924  // If this token is not an isolated token, i.e., it isn't separated from925  // other tokens (e.g. with whitespace), don't interpret it as a register name.926  if (!Op.IsIsolatedToken)927    return;928 929  if (RegisterPrefix.empty()) {930    std::string LoweredTok = Tok.lower();931    if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))932      Op.SingletonReg = Reg->TheDef;933    return;934  }935 936  if (!Tok.consume_front(RegisterPrefix))937    return;938 939  if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Tok))940    Op.SingletonReg = Reg->TheDef;941 942  // If there is no register prefix (i.e. "%" in "%eax"), then this may943  // be some random non-register token, just ignore it.944}945 946void MatchableInfo::initialize(947    const AsmMatcherInfo &Info,948    SmallPtrSetImpl<const Record *> &SingletonRegisters,949    AsmVariantInfo const &Variant, bool HasMnemonicFirst) {950  AsmVariantID = Variant.AsmVariantNo;951  AsmString = CodeGenInstruction::FlattenAsmStringVariants(952      AsmString, Variant.AsmVariantNo);953 954  tokenizeAsmString(Info, Variant);955 956  // The first token of the instruction is the mnemonic, which must be a957  // simple string, not a $foo variable or a singleton register.958  if (AsmOperands.empty())959    PrintFatalError(TheDef->getLoc(),960                    "Instruction '" + TheDef->getName() + "' has no tokens");961 962  assert(!AsmOperands[0].Token.empty());963  if (HasMnemonicFirst) {964    Mnemonic = AsmOperands[0].Token;965    if (Mnemonic[0] == '$')966      PrintFatalError(TheDef->getLoc(),967                      "Invalid instruction mnemonic '" + Mnemonic + "'!");968 969    // Remove the first operand, it is tracked in the mnemonic field.970    AsmOperands.erase(AsmOperands.begin());971  } else if (AsmOperands[0].Token[0] != '$')972    Mnemonic = AsmOperands[0].Token;973 974  // Compute the require features.975  for (const Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))976    if (const SubtargetFeatureInfo *Feature =977            Info.getSubtargetFeature(Predicate))978      RequiredFeatures.push_back(Feature);979 980  // Collect singleton registers, if used.981  for (MatchableInfo::AsmOperand &Op : AsmOperands) {982    extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);983    if (Op.SingletonReg)984      SingletonRegisters.insert(Op.SingletonReg);985  }986 987  const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");988  if (!DepMask)989    DepMask = TheDef->getValue("ComplexDeprecationPredicate");990 991  HasDeprecation =992      DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;993}994 995/// Append an AsmOperand for the given substring of AsmString.996void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {997  AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));998}999 1000/// tokenizeAsmString - Tokenize a simplified assembly string.1001void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,1002                                      AsmVariantInfo const &Variant) {1003  StringRef String = AsmString;1004  size_t Prev = 0;1005  bool InTok = false;1006  bool IsIsolatedToken = true;1007  for (size_t i = 0, e = String.size(); i != e; ++i) {1008    char Char = String[i];1009    if (Variant.BreakCharacters.contains(Char)) {1010      if (InTok) {1011        addAsmOperand(String.substr(Prev, i - Prev), false);1012        Prev = i;1013        IsIsolatedToken = false;1014      }1015      InTok = true;1016      continue;1017    }1018    if (Variant.TokenizingCharacters.contains(Char)) {1019      if (InTok) {1020        addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken);1021        InTok = false;1022        IsIsolatedToken = false;1023      }1024      addAsmOperand(String.substr(i, 1), IsIsolatedToken);1025      Prev = i + 1;1026      IsIsolatedToken = true;1027      continue;1028    }1029    if (Variant.SeparatorCharacters.contains(Char)) {1030      if (InTok) {1031        addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken);1032        InTok = false;1033      }1034      Prev = i + 1;1035      IsIsolatedToken = true;1036      continue;1037    }1038 1039    switch (Char) {1040    case '\\':1041      if (InTok) {1042        addAsmOperand(String.substr(Prev, i - Prev), false);1043        InTok = false;1044        IsIsolatedToken = false;1045      }1046      ++i;1047      assert(i != String.size() && "Invalid quoted character");1048      addAsmOperand(String.substr(i, 1), IsIsolatedToken);1049      Prev = i + 1;1050      IsIsolatedToken = false;1051      break;1052 1053    case '$': {1054      if (InTok) {1055        addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken);1056        InTok = false;1057        IsIsolatedToken = false;1058      }1059 1060      // If this isn't "${", start new identifier looking like "$xxx"1061      if (i + 1 == String.size() || String[i + 1] != '{') {1062        Prev = i;1063        break;1064      }1065 1066      size_t EndPos = String.find('}', i);1067      assert(EndPos != StringRef::npos &&1068             "Missing brace in operand reference!");1069      addAsmOperand(String.substr(i, EndPos + 1 - i), IsIsolatedToken);1070      Prev = EndPos + 1;1071      i = EndPos;1072      IsIsolatedToken = false;1073      break;1074    }1075 1076    default:1077      InTok = true;1078      break;1079    }1080  }1081  if (InTok && Prev != String.size())1082    addAsmOperand(String.substr(Prev), IsIsolatedToken);1083}1084 1085bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {1086  // Reject matchables with no .s string.1087  if (AsmString.empty())1088    PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");1089 1090  // Reject any matchables with a newline in them, they should be marked1091  // isCodeGenOnly if they are pseudo instructions.1092  if (AsmString.find('\n') != std::string::npos)1093    PrintFatalError(TheDef->getLoc(),1094                    "multiline instruction is not valid for the asmparser, "1095                    "mark it isCodeGenOnly");1096 1097  // Remove comments from the asm string.  We know that the asmstring only1098  // has one line.1099  if (!CommentDelimiter.empty() &&1100      StringRef(AsmString).contains(CommentDelimiter))1101    PrintFatalError(TheDef->getLoc(),1102                    "asmstring for instruction has comment character in it, "1103                    "mark it isCodeGenOnly");1104 1105  // Reject matchables with operand modifiers, these aren't something we can1106  // handle, the target should be refactored to use operands instead of1107  // modifiers.1108  //1109  // Also, check for instructions which reference the operand multiple times,1110  // if they don't define a custom AsmMatcher: this implies a constraint that1111  // the built-in matching code would not honor.1112  std::set<std::string> OperandNames;1113  for (const AsmOperand &Op : AsmOperands) {1114    StringRef Tok = Op.Token;1115    if (Tok[0] == '$' && Tok.contains(':'))1116      PrintFatalError(1117          TheDef->getLoc(),1118          "matchable with operand modifier '" + Tok +1119              "' not supported by asm matcher.  Mark isCodeGenOnly!");1120    // Verify that any operand is only mentioned once.1121    // We reject aliases and ignore instructions for now.1122    if (!IsAlias && TheDef->getValueAsString("AsmMatchConverter").empty() &&1123        Tok[0] == '$' && !OperandNames.insert(Tok.str()).second) {1124      LLVM_DEBUG({1125        errs() << "warning: '" << TheDef->getName() << "': "1126               << "ignoring instruction with tied operand '" << Tok << "'\n";1127      });1128      return false;1129    }1130  }1131 1132  return true;1133}1134 1135static std::string getEnumNameForToken(StringRef Str) {1136  std::string Res;1137 1138  for (char C : Str) {1139    switch (C) {1140    case '*':1141      Res += "_STAR_";1142      break;1143    case '%':1144      Res += "_PCT_";1145      break;1146    case ':':1147      Res += "_COLON_";1148      break;1149    case '!':1150      Res += "_EXCLAIM_";1151      break;1152    case '.':1153      Res += "_DOT_";1154      break;1155    case '<':1156      Res += "_LT_";1157      break;1158    case '>':1159      Res += "_GT_";1160      break;1161    case '-':1162      Res += "_MINUS_";1163      break;1164    case '#':1165      Res += "_HASH_";1166      break;1167    default:1168      if (isAlnum(C))1169        Res += C;1170      else1171        Res += "_" + utostr((unsigned)C) + "_";1172    }1173  }1174 1175  return Res;1176}1177 1178ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {1179  ClassInfo *&Entry = TokenClasses[Token.str()];1180 1181  if (!Entry) {1182    Classes.emplace_front();1183    Entry = &Classes.front();1184    Entry->Kind = ClassInfo::Token;1185    Entry->ClassName = "Token";1186    Entry->Name = "MCK_" + getEnumNameForToken(Token);1187    Entry->ValueName = Token.str();1188    Entry->PredicateMethod = "<invalid>";1189    Entry->RenderMethod = "<invalid>";1190    Entry->ParserMethod = "";1191    Entry->DiagnosticType = "";1192    Entry->IsOptional = false;1193    Entry->DefaultMethod = "<invalid>";1194  }1195 1196  return Entry;1197}1198 1199ClassInfo *1200AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,1201                                int SubOpIdx) {1202  const Record *Rec = OI.Rec;1203  if (SubOpIdx != -1)1204    Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();1205  return getOperandClass(Rec, SubOpIdx);1206}1207 1208ClassInfo *AsmMatcherInfo::getOperandClass(const Record *Rec, int SubOpIdx) {1209  if (Rec->isSubClassOf("RegisterOperand")) {1210    // RegisterOperand may have an associated ParserMatchClass. If it does,1211    // use it, else just fall back to the underlying register class.1212    const RecordVal *R = Rec->getValue("ParserMatchClass");1213    if (!R || !R->getValue())1214      PrintFatalError(Rec->getLoc(),1215                      "Record `" + Rec->getName() +1216                          "' does not have a ParserMatchClass!\n");1217 1218    if (const DefInit *DI = dyn_cast<DefInit>(R->getValue())) {1219      const Record *MatchClass = DI->getDef();1220      if (ClassInfo *CI = AsmOperandClasses[MatchClass])1221        return CI;1222    }1223 1224    // No custom match class. Just use the register class.1225    const Record *ClassRec = Rec->getValueAsDef("RegClass");1226    if (!ClassRec)1227      PrintFatalError(Rec->getLoc(),1228                      "RegisterOperand `" + Rec->getName() +1229                          "' has no associated register class!\n");1230 1231    if (ClassRec->isSubClassOf("RegisterClassLike")) {1232      if (ClassInfo *CI = RegisterClassClasses[ClassRec])1233        return CI;1234 1235      PrintFatalError(Rec->getLoc(), "register class has no class info!");1236    }1237  }1238 1239  if (Rec->isSubClassOf("RegisterClass")) {1240    if (ClassInfo *CI = RegisterClassClasses[Rec])1241      return CI;1242    PrintFatalError(Rec->getLoc(), "register class has no class info!");1243  }1244 1245  if (Rec->isSubClassOf("Operand")) {1246    const Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");1247    if (ClassInfo *CI = AsmOperandClasses[MatchClass])1248      return CI;1249  } else if (Rec->isSubClassOf("RegisterClassLike")) {1250    if (ClassInfo *CI = RegisterClassClasses[Rec])1251      return CI;1252    PrintFatalError(Rec->getLoc(), "register class has no class info!");1253  } else {1254    PrintFatalError(Rec->getLoc(),1255                    "Operand `" + Rec->getName() +1256                        "' does not derive from class Operand!\n");1257  }1258 1259  PrintFatalError(Rec->getLoc(), "operand has no match class!");1260}1261 1262struct LessRegisterSet {1263  bool operator()(const RegisterSet &LHS, const RegisterSet &RHS) const {1264    // std::set<T> defines its own compariso "operator<", but it1265    // performs a lexicographical comparison by T's innate comparison1266    // for some reason. We don't want non-deterministic pointer1267    // comparisons so use this instead.1268    return std::lexicographical_compare(LHS.begin(), LHS.end(), RHS.begin(),1269                                        RHS.end(), LessRecordByID());1270  }1271};1272 1273void AsmMatcherInfo::buildRegisterClasses(1274    SmallPtrSetImpl<const Record *> &SingletonRegisters) {1275  const auto &Registers = Target.getRegBank().getRegisters();1276  auto &RegClassList = Target.getRegBank().getRegClasses();1277 1278  using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>;1279 1280  // The register sets used for matching.1281  RegisterSetSet RegisterSets;1282 1283  // Gather the defined sets.1284  for (const CodeGenRegisterClass &RC : RegClassList)1285    RegisterSets.insert(1286        RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));1287 1288  // Add any required singleton sets.1289  for (const Record *Rec : SingletonRegisters) {1290    RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));1291  }1292 1293  // Introduce derived sets where necessary (when a register does not determine1294  // a unique register set class), and build the mapping of registers to the set1295  // they should classify to.1296  std::map<const Record *, RegisterSet> RegisterMap;1297  for (const CodeGenRegister &CGR : Registers) {1298    // Compute the intersection of all sets containing this register.1299    RegisterSet ContainingSet;1300 1301    for (const RegisterSet &RS : RegisterSets) {1302      if (!RS.count(CGR.TheDef))1303        continue;1304 1305      if (ContainingSet.empty()) {1306        ContainingSet = RS;1307        continue;1308      }1309 1310      RegisterSet Tmp;1311      std::set_intersection(ContainingSet.begin(), ContainingSet.end(),1312                            RS.begin(), RS.end(),1313                            std::inserter(Tmp, Tmp.begin()), LessRecordByID());1314      ContainingSet = std::move(Tmp);1315    }1316 1317    if (!ContainingSet.empty()) {1318      RegisterSets.insert(ContainingSet);1319      RegisterMap.try_emplace(CGR.TheDef, ContainingSet);1320    }1321  }1322 1323  // Construct the register classes.1324  std::map<RegisterSet, ClassInfo *, LessRegisterSet> RegisterSetClasses;1325  unsigned Index = 0;1326  for (const RegisterSet &RS : RegisterSets) {1327    Classes.emplace_front();1328    ClassInfo *CI = &Classes.front();1329    CI->Kind = ClassInfo::RegisterClass0 + Index;1330    CI->ClassName = "Reg" + utostr(Index);1331    CI->Name = "MCK_Reg" + utostr(Index);1332    CI->ValueName = "";1333    CI->PredicateMethod = ""; // unused1334    CI->RenderMethod = "addRegOperands";1335    CI->Registers = RS;1336    // FIXME: diagnostic type.1337    CI->DiagnosticType = "";1338    CI->IsOptional = false;1339    CI->DefaultMethod = ""; // unused1340    RegisterSetClasses.try_emplace(RS, CI);1341    ++Index;1342    assert(CI->isRegisterClass());1343  }1344 1345  // Find the superclasses; we could compute only the subgroup lattice edges,1346  // but there isn't really a point.1347  for (const RegisterSet &RS : RegisterSets) {1348    ClassInfo *CI = RegisterSetClasses[RS];1349    for (const RegisterSet &RS2 : RegisterSets)1350      if (RS != RS2 && llvm::includes(RS2, RS, LessRecordByID()))1351        CI->SuperClasses.push_back(RegisterSetClasses[RS2]);1352  }1353 1354  // Name the register classes which correspond to a user defined RegisterClass.1355  for (const CodeGenRegisterClass &RC : RegClassList) {1356    // Def will be NULL for non-user defined register classes.1357    const Record *Def = RC.getDef();1358    if (!Def)1359      continue;1360    ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),1361                                                   RC.getOrder().end())];1362    if (CI->ValueName.empty()) {1363      CI->ClassName = RC.getName();1364      CI->Name = "MCK_" + RC.getName();1365      CI->ValueName = RC.getName();1366    } else {1367      CI->ValueName = CI->ValueName + "," + RC.getName();1368    }1369 1370    const Init *DiagnosticType = Def->getValueInit("DiagnosticType");1371    if (const StringInit *SI = dyn_cast<StringInit>(DiagnosticType))1372      CI->DiagnosticType = SI->getValue().str();1373 1374    const Init *DiagnosticString = Def->getValueInit("DiagnosticString");1375    if (const StringInit *SI = dyn_cast<StringInit>(DiagnosticString))1376      CI->DiagnosticString = SI->getValue().str();1377 1378    // If we have a diagnostic string but the diagnostic type is not specified1379    // explicitly, create an anonymous diagnostic type.1380    if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())1381      CI->DiagnosticType = RC.getName();1382 1383    RegisterClassClasses.try_emplace(Def, CI);1384    assert(CI->isRegisterClass());1385  }1386 1387  unsigned RegClassByHwModeIndex = 0;1388  for (const Record *ClassByHwMode : Target.getAllRegClassByHwMode()) {1389    ClassInfo &CI = Classes.emplace_front();1390    CI.Kind = ClassInfo::RegisterClassByHwMode0 + RegClassByHwModeIndex;1391 1392    CI.ClassName = "RegByHwMode_" + ClassByHwMode->getName().str();1393    CI.Name = "MCK_" + CI.ClassName;1394    CI.ValueName = ClassByHwMode->getName();1395    CI.RenderMethod = "addRegOperands";1396    //  FIXME: Set diagnostic type.1397    ++RegClassByHwModeIndex;1398 1399    assert(CI.isRegisterClassByHwMode());1400 1401    RegisterClassClasses.try_emplace(ClassByHwMode, &CI);1402  }1403 1404  // Populate the map for individual registers.1405  for (auto &It : RegisterMap)1406    RegisterClasses[It.first] = RegisterSetClasses[It.second];1407 1408  // Name the register classes which correspond to singleton registers.1409  for (const Record *Rec : SingletonRegisters) {1410    ClassInfo *CI = RegisterClasses[Rec];1411    assert(CI && "Missing singleton register class info!");1412 1413    if (CI->ValueName.empty()) {1414      CI->ClassName = Rec->getName().str();1415      CI->Name = "MCK_" + Rec->getName().str();1416      CI->ValueName = Rec->getName().str();1417    } else {1418      CI->ValueName = CI->ValueName + "," + Rec->getName().str();1419    }1420  }1421}1422 1423void AsmMatcherInfo::buildOperandClasses() {1424  ArrayRef<const Record *> AsmOperands =1425      Records.getAllDerivedDefinitions("AsmOperandClass");1426 1427  // Pre-populate AsmOperandClasses map.1428  for (const Record *Rec : AsmOperands) {1429    Classes.emplace_front();1430    AsmOperandClasses[Rec] = &Classes.front();1431  }1432 1433  unsigned Index = 0;1434  for (const Record *Rec : AsmOperands) {1435    ClassInfo *CI = AsmOperandClasses[Rec];1436    CI->Kind = ClassInfo::UserClass0 + Index;1437 1438    const ListInit *Supers = Rec->getValueAsListInit("SuperClasses");1439    for (const Init *I : Supers->getElements()) {1440      const DefInit *DI = dyn_cast<DefInit>(I);1441      if (!DI) {1442        PrintError(Rec->getLoc(), "Invalid super class reference!");1443        continue;1444      }1445 1446      ClassInfo *SC = AsmOperandClasses[DI->getDef()];1447      if (!SC)1448        PrintError(Rec->getLoc(), "Invalid super class reference!");1449      else1450        CI->SuperClasses.push_back(SC);1451    }1452    CI->ClassName = Rec->getValueAsString("Name").str();1453    CI->Name = "MCK_" + CI->ClassName;1454    CI->ValueName = Rec->getName().str();1455 1456    // Get or construct the predicate method name.1457    const Init *PMName = Rec->getValueInit("PredicateMethod");1458    if (const StringInit *SI = dyn_cast<StringInit>(PMName)) {1459      CI->PredicateMethod = SI->getValue().str();1460    } else {1461      assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");1462      CI->PredicateMethod = "is" + CI->ClassName;1463    }1464 1465    // Get or construct the render method name.1466    const Init *RMName = Rec->getValueInit("RenderMethod");1467    if (const StringInit *SI = dyn_cast<StringInit>(RMName)) {1468      CI->RenderMethod = SI->getValue().str();1469    } else {1470      assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");1471      CI->RenderMethod = "add" + CI->ClassName + "Operands";1472    }1473 1474    // Get the parse method name or leave it as empty.1475    const Init *PRMName = Rec->getValueInit("ParserMethod");1476    if (const StringInit *SI = dyn_cast<StringInit>(PRMName))1477      CI->ParserMethod = SI->getValue().str();1478 1479    // Get the diagnostic type and string or leave them as empty.1480    const Init *DiagnosticType = Rec->getValueInit("DiagnosticType");1481    if (const StringInit *SI = dyn_cast<StringInit>(DiagnosticType))1482      CI->DiagnosticType = SI->getValue().str();1483    const Init *DiagnosticString = Rec->getValueInit("DiagnosticString");1484    if (const StringInit *SI = dyn_cast<StringInit>(DiagnosticString))1485      CI->DiagnosticString = SI->getValue().str();1486    // If we have a DiagnosticString, we need a DiagnosticType for use within1487    // the matcher.1488    if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())1489      CI->DiagnosticType = CI->ClassName;1490 1491    const Init *IsOptional = Rec->getValueInit("IsOptional");1492    if (const BitInit *BI = dyn_cast<BitInit>(IsOptional))1493      CI->IsOptional = BI->getValue();1494 1495    // Get or construct the default method name.1496    const Init *DMName = Rec->getValueInit("DefaultMethod");1497    if (const StringInit *SI = dyn_cast<StringInit>(DMName)) {1498      CI->DefaultMethod = SI->getValue().str();1499    } else {1500      assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");1501      CI->DefaultMethod = "default" + CI->ClassName + "Operands";1502    }1503 1504    ++Index;1505  }1506}1507 1508AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser,1509                               const CodeGenTarget &target,1510                               const RecordKeeper &records)1511    : Records(records), AsmParser(asmParser), Target(target) {}1512 1513/// buildOperandMatchInfo - Build the necessary information to handle user1514/// defined operand parsing methods.1515void AsmMatcherInfo::buildOperandMatchInfo() {1516  /// Map containing a mask with all operands indices that can be found for1517  /// that class inside a instruction.1518  using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>;1519  OpClassMaskTy OpClassMask;1520 1521  bool CallCustomParserForAllOperands =1522      AsmParser->getValueAsBit("CallCustomParserForAllOperands");1523  for (const auto &MI : Matchables) {1524    OpClassMask.clear();1525 1526    // Keep track of all operands of this instructions which belong to the1527    // same class.1528    unsigned NumOptionalOps = 0;1529    for (const auto &[Idx, Op] : enumerate(MI->AsmOperands)) {1530      if (CallCustomParserForAllOperands || !Op.Class->ParserMethod.empty()) {1531        unsigned &OperandMask = OpClassMask[Op.Class];1532        OperandMask |= maskTrailingOnes<unsigned>(NumOptionalOps + 1)1533                       << (Idx - NumOptionalOps);1534      }1535      if (Op.Class->IsOptional)1536        ++NumOptionalOps;1537    }1538 1539    // Generate operand match info for each mnemonic/operand class pair.1540    for (const auto [CI, OpMask] : OpClassMask) {1541      OperandMatchInfo.push_back(1542          OperandMatchEntry::create(MI.get(), CI, OpMask));1543    }1544  }1545}1546 1547void AsmMatcherInfo::buildInfo() {1548  // Build information about all of the AssemblerPredicates.1549  SubtargetFeaturesInfoVec SubtargetFeaturePairs =1550      SubtargetFeatureInfo::getAll(Records);1551  SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),1552                           SubtargetFeaturePairs.end());1553#ifndef NDEBUG1554  for (const auto &Pair : SubtargetFeatures)1555    LLVM_DEBUG(Pair.second.dump());1556#endif // NDEBUG1557 1558  bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");1559  bool ReportMultipleNearMisses =1560      AsmParser->getValueAsBit("ReportMultipleNearMisses");1561 1562  // Parse the instructions; we need to do this first so that we can gather the1563  // singleton register classes.1564  SmallPtrSet<const Record *, 16> SingletonRegisters;1565  unsigned VariantCount = Target.getAsmParserVariantCount();1566  for (unsigned VC = 0; VC != VariantCount; ++VC) {1567    const Record *AsmVariant = Target.getAsmParserVariant(VC);1568    StringRef CommentDelimiter =1569        AsmVariant->getValueAsString("CommentDelimiter");1570    AsmVariantInfo Variant;1571    Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");1572    Variant.TokenizingCharacters =1573        AsmVariant->getValueAsString("TokenizingCharacters");1574    Variant.SeparatorCharacters =1575        AsmVariant->getValueAsString("SeparatorCharacters");1576    Variant.BreakCharacters = AsmVariant->getValueAsString("BreakCharacters");1577    Variant.Name = AsmVariant->getValueAsString("Name");1578    Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");1579 1580    for (const CodeGenInstruction *CGI : Target.getInstructions()) {1581      // If the tblgen -match-prefix option is specified (for tblgen hackers),1582      // filter the set of instructions we consider.1583      if (!CGI->getName().starts_with(MatchPrefix))1584        continue;1585 1586      // Ignore "codegen only" instructions.1587      if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))1588        continue;1589 1590      // Ignore instructions for different instructions1591      StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");1592      if (!V.empty() && V != Variant.Name)1593        continue;1594 1595      auto II = std::make_unique<MatchableInfo>(*CGI);1596 1597      II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);1598 1599      // Ignore instructions which shouldn't be matched and diagnose invalid1600      // instruction definitions with an error.1601      if (!II->validate(CommentDelimiter, false))1602        continue;1603 1604      Matchables.push_back(std::move(II));1605    }1606 1607    // Parse all of the InstAlias definitions and stick them in the list of1608    // matchables.1609    for (const Record *InstAlias :1610         Records.getAllDerivedDefinitions("InstAlias")) {1611      auto Alias = std::make_unique<CodeGenInstAlias>(InstAlias, Target);1612 1613      // If the tblgen -match-prefix option is specified (for tblgen hackers),1614      // filter the set of instruction aliases we consider, based on the target1615      // instruction.1616      if (!Alias->ResultInst->getName().starts_with(MatchPrefix))1617        continue;1618 1619      StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");1620      if (!V.empty() && V != Variant.Name)1621        continue;1622 1623      auto II = std::make_unique<MatchableInfo>(std::move(Alias));1624 1625      II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);1626 1627      // Validate the alias definitions.1628      II->validate(CommentDelimiter, true);1629 1630      Matchables.push_back(std::move(II));1631    }1632  }1633 1634  // Build info for the register classes.1635  buildRegisterClasses(SingletonRegisters);1636 1637  // Build info for the user defined assembly operand classes.1638  buildOperandClasses();1639 1640  // Build the information about matchables, now that we have fully formed1641  // classes.1642  std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;1643  for (auto &II : Matchables) {1644    // Parse the tokens after the mnemonic.1645    // Note: buildInstructionOperandReference may insert new AsmOperands, so1646    // don't precompute the loop bound, i.e., cannot use range based for loop1647    // here.1648    for (size_t Idx = 0; Idx < II->AsmOperands.size(); ++Idx) {1649      MatchableInfo::AsmOperand &Op = II->AsmOperands[Idx];1650      StringRef Token = Op.Token;1651      // Check for singleton registers.1652      if (const Record *RegRecord = Op.SingletonReg) {1653        Op.Class = RegisterClasses[RegRecord];1654        assert(Op.Class && Op.Class->Registers.size() == 1 &&1655               "Unexpected class for singleton register");1656        continue;1657      }1658 1659      // Check for simple tokens.1660      if (Token[0] != '$') {1661        Op.Class = getTokenClass(Token);1662        continue;1663      }1664 1665      if (Token.size() > 1 && isdigit(Token[1])) {1666        Op.Class = getTokenClass(Token);1667        continue;1668      }1669 1670      // Otherwise this is an operand reference.1671      StringRef OperandName;1672      if (Token[1] == '{')1673        OperandName = Token.substr(2, Token.size() - 3);1674      else1675        OperandName = Token.substr(1);1676 1677      if (isa<const CodeGenInstruction *>(II->DefRec))1678        buildInstructionOperandReference(II.get(), OperandName, Idx);1679      else1680        buildAliasOperandReference(II.get(), OperandName, Op);1681    }1682 1683    if (isa<const CodeGenInstruction *>(II->DefRec)) {1684      II->buildInstructionResultOperands();1685      // If the instruction has a two-operand alias, build up the1686      // matchable here. We'll add them in bulk at the end to avoid1687      // confusing this loop.1688      StringRef Constraint =1689          II->TheDef->getValueAsString("TwoOperandAliasConstraint");1690      if (Constraint != "") {1691        // Start by making a copy of the original matchable.1692        auto AliasII = std::make_unique<MatchableInfo>(*II);1693 1694        // Adjust it to be a two-operand alias.1695        AliasII->formTwoOperandAlias(Constraint);1696 1697        // Add the alias to the matchables list.1698        NewMatchables.push_back(std::move(AliasII));1699      }1700    } else {1701      // FIXME: The tied operands checking is not yet integrated with the1702      // framework for reporting multiple near misses. To prevent invalid1703      // formats from being matched with an alias if a tied-operands check1704      // would otherwise have disallowed it, we just disallow such constructs1705      // in TableGen completely.1706      II->buildAliasResultOperands(!ReportMultipleNearMisses);1707    }1708  }1709  if (!NewMatchables.empty())1710    Matchables.insert(Matchables.end(),1711                      std::make_move_iterator(NewMatchables.begin()),1712                      std::make_move_iterator(NewMatchables.end()));1713 1714  // Process token alias definitions and set up the associated superclass1715  // information.1716  for (const Record *Rec : Records.getAllDerivedDefinitions("TokenAlias")) {1717    ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));1718    ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));1719    if (FromClass == ToClass)1720      PrintFatalError(Rec->getLoc(),1721                      "error: Destination value identical to source value.");1722    FromClass->SuperClasses.push_back(ToClass);1723  }1724 1725  // Reorder classes so that classes precede super classes.1726  Classes.sort();1727 1728#ifdef EXPENSIVE_CHECKS1729  // Verify that the table is sorted and operator < works transitively.1730  for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {1731    for (auto J = I; J != E; ++J) {1732      assert(!(*J < *I));1733      assert(I == J || !J->isSubsetOf(*I));1734    }1735  }1736#endif1737}1738 1739/// buildInstructionOperandReference - The specified operand is a reference to a1740/// named operand such as $src.  Resolve the Class and OperandInfo pointers.1741void AsmMatcherInfo::buildInstructionOperandReference(MatchableInfo *II,1742                                                      StringRef OperandName,1743                                                      unsigned AsmOpIdx) {1744  const CodeGenInstruction &CGI = *cast<const CodeGenInstruction *>(II->DefRec);1745  const CGIOperandList &Operands = CGI.Operands;1746  MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];1747 1748  // Map this token to an operand.1749  std::optional<unsigned> Idx = Operands.findOperandNamed(OperandName);1750  if (!Idx)1751    PrintFatalError(II->TheDef->getLoc(),1752                    "error: unable to find operand: '" + OperandName + "'");1753  // If the instruction operand has multiple suboperands, but the parser1754  // match class for the asm operand is still the default "ImmAsmOperand",1755  // then handle each suboperand separately.1756  if (Op->SubOpIdx == -1 && Operands[*Idx].MINumOperands > 1) {1757    const Record *Rec = Operands[*Idx].Rec;1758    assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");1759    const Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");1760    if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {1761      // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.1762      StringRef Token = Op->Token; // save this in case Op gets moved1763      for (unsigned SI = 1, SE = Operands[*Idx].MINumOperands; SI != SE; ++SI) {1764        MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);1765        NewAsmOp.SubOpIdx = SI;1766        II->AsmOperands.insert(II->AsmOperands.begin() + AsmOpIdx + SI,1767                               NewAsmOp);1768      }1769      // Replace Op with first suboperand.1770      Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved1771      Op->SubOpIdx = 0;1772    }1773  }1774 1775  // Set up the operand class.1776  Op->Class = getOperandClass(Operands[*Idx], Op->SubOpIdx);1777  Op->OrigSrcOpName = OperandName;1778 1779  // If the named operand is tied, canonicalize it to the untied operand.1780  // For example, something like:1781  //   (outs GPR:$dst), (ins GPR:$src)1782  // with an asmstring of1783  //   "inc $src"1784  // we want to canonicalize to:1785  //   "inc $dst"1786  // so that we know how to provide the $dst operand when filling in the result.1787  int OITied = -1;1788  if (Operands[*Idx].MINumOperands == 1)1789    OITied = Operands[*Idx].getTiedRegister();1790  if (OITied != -1) {1791    // The tied operand index is an MIOperand index, find the operand that1792    // contains it.1793    auto [OpIdx, SubopIdx] = Operands.getSubOperandNumber(OITied);1794    OperandName = Operands[OpIdx].Name;1795    Op->SubOpIdx = SubopIdx;1796  }1797 1798  Op->SrcOpName = OperandName;1799}1800 1801/// buildAliasOperandReference - When parsing an operand reference out of the1802/// matching string (e.g. "movsx $src, $dst"), determine what the class of the1803/// operand reference is by looking it up in the result pattern definition.1804void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,1805                                                StringRef OperandName,1806                                                MatchableInfo::AsmOperand &Op) {1807  const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(II->DefRec);1808 1809  // Set up the operand class.1810  for (const auto &[ResultOp, SubOpIdx] :1811       zip_equal(CGA.ResultOperands, CGA.ResultInstOperandIndex)) {1812    if (ResultOp.isRecord() && ResultOp.getName() == OperandName) {1813      // It's safe to go with the first one we find, because CodeGenInstAlias1814      // validates that all operands with the same name have the same record.1815      Op.SubOpIdx = SubOpIdx.second;1816      // Use the match class from the Alias definition, not the1817      // destination instruction, as we may have an immediate that's1818      // being munged by the match class.1819      Op.Class = getOperandClass(ResultOp.getRecord(), Op.SubOpIdx);1820      Op.SrcOpName = OperandName;1821      Op.OrigSrcOpName = OperandName;1822      return;1823    }1824  }1825 1826  PrintFatalError(II->TheDef->getLoc(),1827                  "error: unable to find operand: '" + OperandName + "'");1828}1829 1830void MatchableInfo::buildInstructionResultOperands() {1831  const CodeGenInstruction *ResultInst = getResultInst();1832 1833  // Loop over all operands of the result instruction, determining how to1834  // populate them.1835  for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {1836    // If this is a tied operand, just copy from the previously handled operand.1837    int TiedOp = -1;1838    if (OpInfo.MINumOperands == 1)1839      TiedOp = OpInfo.getTiedRegister();1840    if (TiedOp != -1) {1841      int TiedSrcOperand = findAsmOperandOriginallyNamed(OpInfo.Name);1842      if (TiedSrcOperand != -1 &&1843          ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand)1844        ResOperands.push_back(ResOperand::getTiedOp(1845            TiedOp, ResOperands[TiedOp].AsmOperandNum, TiedSrcOperand));1846      else1847        ResOperands.push_back(ResOperand::getTiedOp(TiedOp, 0, 0));1848      continue;1849    }1850 1851    int SrcOperand = findAsmOperandNamed(OpInfo.Name);1852    if (OpInfo.Name.empty() || SrcOperand == -1) {1853      // This may happen for operands that are tied to a suboperand of a1854      // complex operand.  Simply use a dummy value here; nobody should1855      // use this operand slot.1856      // FIXME: The long term goal is for the MCOperand list to not contain1857      // tied operands at all.1858      ResOperands.push_back(ResOperand::getImmOp(0));1859      continue;1860    }1861 1862    // Check if the one AsmOperand populates the entire operand.1863    unsigned NumOperands = OpInfo.MINumOperands;1864    if (AsmOperands[SrcOperand].SubOpIdx == -1) {1865      ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));1866      continue;1867    }1868 1869    // Add a separate ResOperand for each suboperand.1870    for (unsigned AI = 0; AI < NumOperands; ++AI) {1871      assert(AsmOperands[SrcOperand + AI].SubOpIdx == (int)AI &&1872             AsmOperands[SrcOperand + AI].SrcOpName == OpInfo.Name &&1873             "unexpected AsmOperands for suboperands");1874      ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));1875    }1876  }1877}1878 1879void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {1880  const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(DefRec);1881  const CodeGenInstruction *ResultInst = getResultInst();1882 1883  // Map of:  $reg -> #lastref1884  //   where $reg is the name of the operand in the asm string1885  //   where #lastref is the last processed index where $reg was referenced in1886  //   the asm string.1887  SmallDenseMap<StringRef, int> OperandRefs;1888 1889  // Loop over all operands of the result instruction, determining how to1890  // populate them.1891  unsigned AliasOpNo = 0;1892  unsigned LastOpNo = CGA.ResultInstOperandIndex.size();1893  for (const auto &[Idx, OpInfo] : enumerate(ResultInst->Operands)) {1894    // If this is a tied operand, just copy from the previously handled operand.1895    int TiedOp = -1;1896    if (OpInfo.MINumOperands == 1)1897      TiedOp = OpInfo.getTiedRegister();1898    if (TiedOp != -1) {1899      unsigned SrcOp1 = 0;1900      unsigned SrcOp2 = 0;1901 1902      // If an operand has been specified twice in the asm string,1903      // add the two source operand's indices to the TiedOp so that1904      // at runtime the 'tied' constraint is checked.1905      if (ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand) {1906        SrcOp1 = ResOperands[TiedOp].AsmOperandNum;1907 1908        // Find the next operand (similarly named operand) in the string.1909        StringRef Name = AsmOperands[SrcOp1].SrcOpName;1910        auto Insert = OperandRefs.try_emplace(Name, SrcOp1);1911        SrcOp2 = findAsmOperandNamed(Name, Insert.first->second);1912 1913        // Not updating the record in OperandRefs will cause TableGen1914        // to fail with an error at the end of this function.1915        if (AliasConstraintsAreChecked)1916          Insert.first->second = SrcOp2;1917 1918        // In case it only has one reference in the asm string,1919        // it doesn't need to be checked for tied constraints.1920        SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2;1921      }1922 1923      // If the alias operand is of a different operand class, we only want1924      // to benefit from the tied-operands check and just match the operand1925      // as a normal, but not copy the original (TiedOp) to the result1926      // instruction. We do this by passing -1 as the tied operand to copy.1927      if (OpInfo.Rec->getName() !=1928          ResultInst->Operands[TiedOp].Rec->getName()) {1929        SrcOp1 = ResOperands[TiedOp].AsmOperandNum;1930        int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;1931        StringRef Name = CGA.ResultOperands[AliasOpNo].getName();1932        SrcOp2 = findAsmOperand(Name, SubIdx);1933        ResOperands.push_back(1934            ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2));1935      } else {1936        ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2));1937        continue;1938      }1939    }1940 1941    // Handle all the suboperands for this operand.1942    StringRef OpName = OpInfo.Name;1943    for (; AliasOpNo < LastOpNo &&1944           CGA.ResultInstOperandIndex[AliasOpNo].first == Idx;1945         ++AliasOpNo) {1946      int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;1947 1948      // Find out what operand from the asmparser that this MCInst operand1949      // comes from.1950      switch (CGA.ResultOperands[AliasOpNo].Kind) {1951      case CodeGenInstAlias::ResultOperand::K_Record: {1952        StringRef Name = CGA.ResultOperands[AliasOpNo].getName();1953        int SrcOperand = findAsmOperand(Name, SubIdx);1954        if (SrcOperand == -1)1955          PrintFatalError(TheDef->getLoc(),1956                          "Instruction '" + TheDef->getName() +1957                              "' has operand '" + OpName +1958                              "' that doesn't appear in asm string!");1959 1960        // Add it to the operand references. If it is added a second time, the1961        // record won't be updated and it will fail later on.1962        OperandRefs.try_emplace(Name, SrcOperand);1963 1964        unsigned NumOperands = (SubIdx == -1 ? OpInfo.MINumOperands : 1);1965        ResOperands.push_back(1966            ResOperand::getRenderedOp(SrcOperand, NumOperands));1967        break;1968      }1969      case CodeGenInstAlias::ResultOperand::K_Imm: {1970        int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();1971        ResOperands.push_back(ResOperand::getImmOp(ImmVal));1972        break;1973      }1974      case CodeGenInstAlias::ResultOperand::K_Reg: {1975        const Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();1976        ResOperands.push_back(ResOperand::getRegOp(Reg));1977        break;1978      }1979      }1980    }1981  }1982 1983  // Check that operands are not repeated more times than is supported.1984  for (auto &T : OperandRefs) {1985    if (T.second != -1 && findAsmOperandNamed(T.first, T.second) != -1)1986      PrintFatalError(TheDef->getLoc(),1987                      "Operand '" + T.first + "' can never be matched");1988  }1989}1990 1991static unsigned1992getConverterOperandID(const std::string &Name,1993                      SmallSetVector<CachedHashString, 16> &Table,1994                      bool &IsNew) {1995  IsNew = Table.insert(CachedHashString(Name));1996 1997  unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();1998 1999  assert(ID < Table.size());2000 2001  return ID;2002}2003 2004static unsigned2005emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,2006                 std::vector<std::unique_ptr<MatchableInfo>> &Infos,2007                 bool HasMnemonicFirst, bool HasOptionalOperands,2008                 raw_ostream &OS) {2009  SmallSetVector<CachedHashString, 16> OperandConversionKinds;2010  SmallSetVector<CachedHashString, 16> InstructionConversionKinds;2011  std::vector<std::vector<uint8_t>> ConversionTable;2012  size_t MaxRowLength = 2; // minimum is custom converter plus terminator.2013 2014  // TargetOperandClass - This is the target's operand class, like X86Operand.2015  std::string TargetOperandClass = Target.getName().str() + "Operand";2016 2017  // Write the convert function to a separate stream, so we can drop it after2018  // the enum. We'll build up the conversion handlers for the individual2019  // operand types opportunistically as we encounter them.2020  std::string ConvertFnBody;2021  raw_string_ostream CvtOS(ConvertFnBody);2022  // Start the unified conversion function.2023  if (HasOptionalOperands) {2024    CvtOS << "void " << Target.getName() << ClassName << "::\n"2025          << "convertToMCInst(unsigned Kind, MCInst &Inst, "2026          << "unsigned Opcode,\n"2027          << "                const OperandVector &Operands,\n"2028          << "                const SmallBitVector &OptionalOperandsMask,\n"2029          << "                ArrayRef<unsigned> DefaultsOffset) {\n";2030  } else {2031    CvtOS << "void " << Target.getName() << ClassName << "::\n"2032          << "convertToMCInst(unsigned Kind, MCInst &Inst, "2033          << "unsigned Opcode,\n"2034          << "                const OperandVector &Operands) {\n";2035  }2036  CvtOS << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";2037  CvtOS << "  const uint8_t *Converter = ConversionTable[Kind];\n";2038  CvtOS << "  Inst.setOpcode(Opcode);\n";2039  CvtOS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n";2040  if (HasOptionalOperands) {2041    // When optional operands are involved, formal and actual operand indices2042    // may differ. Map the former to the latter by subtracting the number of2043    // absent optional operands.2044    // FIXME: This is not an operand index in the CVT_Tied case2045    CvtOS << "    unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";2046  } else {2047    CvtOS << "    unsigned OpIdx = *(p + 1);\n";2048  }2049  CvtOS << "    switch (*p) {\n";2050  CvtOS << "    default: llvm_unreachable(\"invalid conversion entry!\");\n";2051  CvtOS << "    case CVT_Reg:\n";2052  CvtOS << "      static_cast<" << TargetOperandClass2053        << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";2054  CvtOS << "      break;\n";2055  CvtOS << "    case CVT_Tied: {\n";2056  CvtOS << "      assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -\n";2057  CvtOS2058      << "                              std::begin(TiedAsmOperandTable)) &&\n";2059  CvtOS << "             \"Tied operand not found\");\n";2060  CvtOS << "      unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];\n";2061  CvtOS << "      if (TiedResOpnd != (uint8_t)-1)\n";2062  CvtOS << "        Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";2063  CvtOS << "      break;\n";2064  CvtOS << "    }\n";2065 2066  std::string OperandFnBody;2067  raw_string_ostream OpOS(OperandFnBody);2068  // Start the operand number lookup function.2069  OpOS << "void " << Target.getName() << ClassName << "::\n"2070       << "convertToMapAndConstraints(unsigned Kind,\n";2071  OpOS.indent(27);2072  OpOS << "const OperandVector &Operands) {\n"2073       << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"2074       << "  unsigned NumMCOperands = 0;\n"2075       << "  const uint8_t *Converter = ConversionTable[Kind];\n"2076       << "  for (const uint8_t *p = Converter; *p; p += 2) {\n"2077       << "    switch (*p) {\n"2078       << "    default: llvm_unreachable(\"invalid conversion entry!\");\n"2079       << "    case CVT_Reg:\n"2080       << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"2081       << "      Operands[*(p + 1)]->setConstraint(\"r\");\n"2082       << "      ++NumMCOperands;\n"2083       << "      break;\n"2084       << "    case CVT_Tied:\n"2085       << "      ++NumMCOperands;\n"2086       << "      break;\n";2087 2088  // Pre-populate the operand conversion kinds with the standard always2089  // available entries.2090  OperandConversionKinds.insert(CachedHashString("CVT_Done"));2091  OperandConversionKinds.insert(CachedHashString("CVT_Reg"));2092  OperandConversionKinds.insert(CachedHashString("CVT_Tied"));2093  enum { CVT_Done, CVT_Reg, CVT_Tied };2094 2095  // Map of e.g. <0, 2, 3> -> "Tie_0_2_3" enum label.2096  std::map<std::tuple<uint8_t, uint8_t, uint8_t>, std::string>2097      TiedOperandsEnumMap;2098 2099  for (auto &II : Infos) {2100    // Check if we have a custom match function.2101    StringRef AsmMatchConverter =2102        II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");2103    if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {2104      std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();2105      II->ConversionFnKind = Signature;2106 2107      // Check if we have already generated this signature.2108      if (!InstructionConversionKinds.insert(CachedHashString(Signature)))2109        continue;2110 2111      // Remember this converter for the kind enum.2112      unsigned KindID = OperandConversionKinds.size();2113      OperandConversionKinds.insert(2114          CachedHashString("CVT_" + getEnumNameForToken(AsmMatchConverter)));2115 2116      // Add the converter row for this instruction.2117      ConversionTable.emplace_back();2118      ConversionTable.back().push_back(KindID);2119      ConversionTable.back().push_back(CVT_Done);2120 2121      // Add the handler to the conversion driver function.2122      CvtOS << "    case CVT_" << getEnumNameForToken(AsmMatchConverter)2123            << ":\n"2124            << "      " << AsmMatchConverter << "(Inst, Operands);\n"2125            << "      break;\n";2126 2127      // FIXME: Handle the operand number lookup for custom match functions.2128      continue;2129    }2130 2131    // Build the conversion function signature.2132    std::string Signature = "Convert";2133 2134    std::vector<uint8_t> ConversionRow;2135 2136    // Compute the convert enum and the case body.2137    MaxRowLength = std::max(MaxRowLength, II->ResOperands.size() * 2 + 1);2138 2139    for (const auto &[Idx, OpInfo] : enumerate(II->ResOperands)) {2140      // Generate code to populate each result operand.2141      switch (OpInfo.Kind) {2142      case MatchableInfo::ResOperand::RenderAsmOperand: {2143        // This comes from something we parsed.2144        const MatchableInfo::AsmOperand &Op =2145            II->AsmOperands[OpInfo.AsmOperandNum];2146 2147        // Registers are always converted the same, don't duplicate the2148        // conversion function based on them.2149        Signature += "__";2150        std::string Class;2151        Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;2152        Signature += Class;2153        Signature += utostr(OpInfo.MINumOperands);2154        Signature += "_" + itostr(OpInfo.AsmOperandNum);2155 2156        // Add the conversion kind, if necessary, and get the associated ID2157        // the index of its entry in the vector).2158        std::string Name =2159            "CVT_" +2160            (Op.Class->isRegisterClass() ? "Reg" : Op.Class->RenderMethod);2161        if (Op.Class->IsOptional) {2162          // For optional operands we must also care about DefaultMethod2163          assert(HasOptionalOperands);2164          Name += "_" + Op.Class->DefaultMethod;2165        }2166        Name = getEnumNameForToken(Name);2167 2168        bool IsNewConverter = false;2169        unsigned ID =2170            getConverterOperandID(Name, OperandConversionKinds, IsNewConverter);2171 2172        // Add the operand entry to the instruction kind conversion row.2173        ConversionRow.push_back(ID);2174        ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);2175 2176        if (!IsNewConverter)2177          break;2178 2179        // This is a new operand kind. Add a handler for it to the2180        // converter driver.2181        CvtOS << "    case " << Name << ":\n";2182        if (Op.Class->IsOptional) {2183          // If optional operand is not present in actual instruction then we2184          // should call its DefaultMethod before RenderMethod2185          assert(HasOptionalOperands);2186          CvtOS << "      if (OptionalOperandsMask[*(p + 1) - 1]) {\n"2187                << "        " << Op.Class->DefaultMethod << "()"2188                << "->" << Op.Class->RenderMethod << "(Inst, "2189                << OpInfo.MINumOperands << ");\n"2190                << "      } else {\n"2191                << "        static_cast<" << TargetOperandClass2192                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod2193                << "(Inst, " << OpInfo.MINumOperands << ");\n"2194                << "      }\n";2195        } else {2196          CvtOS << "      static_cast<" << TargetOperandClass2197                << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod2198                << "(Inst, " << OpInfo.MINumOperands << ");\n";2199        }2200        CvtOS << "      break;\n";2201 2202        // Add a handler for the operand number lookup.2203        OpOS << "    case " << Name << ":\n"2204             << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";2205 2206        if (Op.Class->isRegisterClass())2207          OpOS << "      Operands[*(p + 1)]->setConstraint(\"r\");\n";2208        else2209          OpOS << "      Operands[*(p + 1)]->setConstraint(\"m\");\n";2210        OpOS << "      NumMCOperands += " << OpInfo.MINumOperands << ";\n"2211             << "      break;\n";2212        break;2213      }2214      case MatchableInfo::ResOperand::TiedOperand: {2215        // If this operand is tied to a previous one, just copy the MCInst2216        // operand from the earlier one.We can only tie single MCOperand values.2217        assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");2218        uint8_t TiedOp = OpInfo.TiedOperands.ResOpnd;2219        uint8_t SrcOp1 = OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst;2220        uint8_t SrcOp2 = OpInfo.TiedOperands.SrcOpnd2Idx + HasMnemonicFirst;2221        assert((Idx > TiedOp || TiedOp == (uint8_t)-1) &&2222               "Tied operand precedes its target!");2223        auto TiedTupleName = std::string("Tie") + utostr(TiedOp) + '_' +2224                             utostr(SrcOp1) + '_' + utostr(SrcOp2);2225        Signature += "__" + TiedTupleName;2226        ConversionRow.push_back(CVT_Tied);2227        ConversionRow.push_back(TiedOp);2228        ConversionRow.push_back(SrcOp1);2229        ConversionRow.push_back(SrcOp2);2230 2231        // Also create an 'enum' for this combination of tied operands.2232        auto Key = std::tuple(TiedOp, SrcOp1, SrcOp2);2233        TiedOperandsEnumMap.emplace(Key, TiedTupleName);2234        break;2235      }2236      case MatchableInfo::ResOperand::ImmOperand: {2237        int64_t Val = OpInfo.ImmVal;2238        std::string Ty = "imm_" + itostr(Val);2239        Ty = getEnumNameForToken(Ty);2240        Signature += "__" + Ty;2241 2242        std::string Name = "CVT_" + Ty;2243        bool IsNewConverter = false;2244        unsigned ID =2245            getConverterOperandID(Name, OperandConversionKinds, IsNewConverter);2246        // Add the operand entry to the instruction kind conversion row.2247        ConversionRow.push_back(ID);2248        ConversionRow.push_back(0);2249 2250        if (!IsNewConverter)2251          break;2252 2253        CvtOS << "    case " << Name << ":\n"2254              << "      Inst.addOperand(MCOperand::createImm(" << Val << "));\n"2255              << "      break;\n";2256 2257        OpOS << "    case " << Name << ":\n"2258             << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"2259             << "      Operands[*(p + 1)]->setConstraint(\"\");\n"2260             << "      ++NumMCOperands;\n"2261             << "      break;\n";2262        break;2263      }2264      case MatchableInfo::ResOperand::RegOperand: {2265        std::string Reg, Name;2266        if (!OpInfo.Register) {2267          Name = "reg0";2268          Reg = "0";2269        } else {2270          Reg = getQualifiedName(OpInfo.Register);2271          Name = "reg" + OpInfo.Register->getName().str();2272        }2273        Signature += "__" + Name;2274        Name = "CVT_" + Name;2275        bool IsNewConverter = false;2276        unsigned ID =2277            getConverterOperandID(Name, OperandConversionKinds, IsNewConverter);2278        // Add the operand entry to the instruction kind conversion row.2279        ConversionRow.push_back(ID);2280        ConversionRow.push_back(0);2281 2282        if (!IsNewConverter)2283          break;2284        CvtOS << "    case " << Name << ":\n"2285              << "      Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"2286              << "      break;\n";2287 2288        OpOS << "    case " << Name << ":\n"2289             << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"2290             << "      Operands[*(p + 1)]->setConstraint(\"m\");\n"2291             << "      ++NumMCOperands;\n"2292             << "      break;\n";2293      }2294      }2295    }2296 2297    // If there were no operands, add to the signature to that effect2298    if (Signature == "Convert")2299      Signature += "_NoOperands";2300 2301    II->ConversionFnKind = Signature;2302 2303    // Save the signature. If we already have it, don't add a new row2304    // to the table.2305    if (!InstructionConversionKinds.insert(CachedHashString(Signature)))2306      continue;2307 2308    // Add the row to the table.2309    ConversionTable.push_back(std::move(ConversionRow));2310  }2311 2312  // Finish up the converter driver function.2313  CvtOS << "    }\n  }\n}\n\n";2314 2315  // Finish up the operand number lookup function.2316  OpOS << "    }\n  }\n}\n\n";2317 2318  // Output a static table for tied operands.2319  if (TiedOperandsEnumMap.size()) {2320    // The number of tied operand combinations will be small in practice,2321    // but just add the assert to be sure.2322    assert(TiedOperandsEnumMap.size() <= 254 &&2323           "Too many tied-operand combinations to reference with "2324           "an 8bit offset from the conversion table, where index "2325           "'255' is reserved as operand not to be copied.");2326 2327    OS << "enum {\n";2328    for (auto &KV : TiedOperandsEnumMap) {2329      OS << "  " << KV.second << ",\n";2330    }2331    OS << "};\n\n";2332 2333    OS << "static const uint8_t TiedAsmOperandTable[][3] = {\n";2334    for (auto &KV : TiedOperandsEnumMap) {2335      OS << "  /* " << KV.second << " */ { " << utostr(std::get<0>(KV.first))2336         << ", " << utostr(std::get<1>(KV.first)) << ", "2337         << utostr(std::get<2>(KV.first)) << " },\n";2338    }2339    OS << "};\n\n";2340  } else {2341    OS << "static const uint8_t TiedAsmOperandTable[][3] = "2342          "{ /* empty  */ {0, 0, 0} };\n\n";2343  }2344 2345  OS << "namespace {\n";2346 2347  // Output the operand conversion kind enum.2348  OS << "enum OperatorConversionKind {\n";2349  for (const auto &Converter : OperandConversionKinds)2350    OS << "  " << Converter << ",\n";2351  OS << "  CVT_NUM_CONVERTERS\n";2352  OS << "};\n\n";2353 2354  // Output the instruction conversion kind enum.2355  OS << "enum InstructionConversionKind {\n";2356  for (const auto &Signature : InstructionConversionKinds)2357    OS << "  " << Signature << ",\n";2358  OS << "  CVT_NUM_SIGNATURES\n";2359  OS << "};\n\n";2360 2361  OS << "} // end anonymous namespace\n\n";2362 2363  // Output the conversion table.2364  OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["2365     << MaxRowLength << "] = {\n";2366 2367  for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {2368    assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");2369    OS << "  // " << InstructionConversionKinds[Row] << "\n";2370    OS << "  { ";2371    for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) {2372      const auto &OCK = OperandConversionKinds[ConversionTable[Row][i]];2373      OS << OCK << ", ";2374      if (OCK != CachedHashString("CVT_Tied")) {2375        OS << (unsigned)(ConversionTable[Row][i + 1]) << ", ";2376        continue;2377      }2378 2379      // For a tied operand, emit a reference to the TiedAsmOperandTable2380      // that contains the operand to copy, and the parsed operands to2381      // check for their tied constraints.2382      auto Key = std::tuple((uint8_t)ConversionTable[Row][i + 1],2383                            (uint8_t)ConversionTable[Row][i + 2],2384                            (uint8_t)ConversionTable[Row][i + 3]);2385      auto TiedOpndEnum = TiedOperandsEnumMap.find(Key);2386      assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&2387             "No record for tied operand pair");2388      OS << TiedOpndEnum->second << ", ";2389      i += 2;2390    }2391    OS << "CVT_Done },\n";2392  }2393 2394  OS << "};\n\n";2395 2396  // Spit out the conversion driver function.2397  OS << ConvertFnBody;2398 2399  // Spit out the operand number lookup function.2400  OS << OperandFnBody;2401 2402  return ConversionTable.size();2403}2404 2405/// emitMatchClassEnumeration - Emit the enumeration for match class kinds.2406static void emitMatchClassEnumeration(CodeGenTarget &Target,2407                                      std::forward_list<ClassInfo> &Infos,2408                                      raw_ostream &OS) {2409  OS << "namespace {\n\n";2410 2411  OS << "/// MatchClassKind - The kinds of classes which participate in\n"2412     << "/// instruction matching.\n";2413  OS << "enum MatchClassKind {\n";2414  OS << "  InvalidMatchClass = 0,\n";2415  OS << "  OptionalMatchClass = 1,\n";2416  ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;2417  StringRef LastName = "OptionalMatchClass";2418  for (const auto &CI : Infos) {2419    if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {2420      OS << "  MCK_LAST_TOKEN = " << LastName << ",\n";2421    } else if (LastKind < ClassInfo::RegisterClassByHwMode0 &&2422               CI.Kind >= ClassInfo::RegisterClassByHwMode0) {2423      OS << "  MCK_LAST_REGISTER = " << LastName << ",\n";2424    } else if (LastKind < ClassInfo::UserClass0 &&2425               CI.Kind >= ClassInfo::UserClass0) {2426      OS << "  MCK_LAST_REGCLASS_BY_HWMODE = " << LastName << ",\n";2427    }2428 2429    LastKind = (ClassInfo::ClassInfoKind)CI.Kind;2430    LastName = CI.Name;2431 2432    OS << "  " << CI.Name << ", // ";2433    if (CI.Kind == ClassInfo::Token) {2434      OS << "'" << CI.ValueName << "'\n";2435    } else if (CI.isRegisterClass()) {2436      if (!CI.ValueName.empty())2437        OS << "register class '" << CI.ValueName << "'\n";2438      else2439        OS << "derived register class\n";2440    } else if (CI.isRegisterClassByHwMode()) {2441      OS << "register class by hwmode\n";2442    } else {2443      OS << "user defined class '" << CI.ValueName << "'\n";2444    }2445  }2446  OS << "  NumMatchClassKinds\n";2447  OS << "};\n\n";2448 2449  OS << "} // end anonymous namespace\n\n";2450}2451 2452/// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be2453/// used when an assembly operand does not match the expected operand class.2454static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info,2455                                             raw_ostream &OS) {2456  // If the target does not use DiagnosticString for any operands, don't emit2457  // an unused function.2458  if (llvm::all_of(Info.Classes, [](const ClassInfo &CI) {2459        return CI.DiagnosticString.empty();2460      }))2461    return;2462 2463  OS << "static const char *getMatchKindDiag(" << Info.Target.getName()2464     << "AsmParser::" << Info.Target.getName()2465     << "MatchResultTy MatchResult) {\n";2466  OS << "  switch (MatchResult) {\n";2467 2468  for (const auto &CI : Info.Classes) {2469    if (!CI.DiagnosticString.empty()) {2470      assert(!CI.DiagnosticType.empty() &&2471             "DiagnosticString set without DiagnosticType");2472      OS << "  case " << Info.Target.getName() << "AsmParser::Match_"2473         << CI.DiagnosticType << ":\n";2474      OS << "    return \"" << CI.DiagnosticString << "\";\n";2475    }2476  }2477 2478  OS << "  default:\n";2479  OS << "    return nullptr;\n";2480 2481  OS << "  }\n";2482  OS << "}\n\n";2483}2484 2485static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {2486  OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "2487        "RegisterClass) {\n";2488  if (none_of(Info.Classes, [](const ClassInfo &CI) {2489        return CI.isRegisterClass() && !CI.DiagnosticType.empty();2490      })) {2491    OS << "  return MCTargetAsmParser::Match_InvalidOperand;\n";2492  } else {2493    OS << "  switch (RegisterClass) {\n";2494    for (const auto &CI : Info.Classes) {2495      if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {2496        OS << "  case " << CI.Name << ":\n";2497        OS << "    return " << Info.Target.getName() << "AsmParser::Match_"2498           << CI.DiagnosticType << ";\n";2499      }2500    }2501 2502    OS << "  default:\n";2503    OS << "    return MCTargetAsmParser::Match_InvalidOperand;\n";2504 2505    OS << "  }\n";2506  }2507  OS << "}\n\n";2508}2509 2510/// emitValidateOperandClass - Emit the function to validate an operand class.2511static void emitValidateOperandClass(const CodeGenTarget &Target,2512                                     AsmMatcherInfo &Info, raw_ostream &OS) {2513  OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "2514     << "MatchClassKind Kind, const MCSubtargetInfo &STI) {\n";2515  OS << "  " << Info.Target.getName() << "Operand &Operand = ("2516     << Info.Target.getName() << "Operand &)GOp;\n";2517 2518  // The InvalidMatchClass is not to match any operand.2519  OS << "  if (Kind == InvalidMatchClass)\n";2520  OS << "    return MCTargetAsmParser::Match_InvalidOperand;\n\n";2521 2522  // Check for Token operands first.2523  // FIXME: Use a more specific diagnostic type.2524  OS << "  if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)\n";2525  OS << "    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"2526     << "             MCTargetAsmParser::Match_Success :\n"2527     << "             MCTargetAsmParser::Match_InvalidOperand;\n\n";2528 2529  // Check the user classes. We don't care what order since we're only2530  // actually matching against one of them.2531  OS << "  switch (Kind) {\n"2532        "  default: break;\n";2533  for (const auto &CI : Info.Classes) {2534    if (!CI.isUserClass())2535      continue;2536 2537    OS << "  case " << CI.Name << ": {\n";2538    OS << "    DiagnosticPredicate DP(Operand." << CI.PredicateMethod2539       << "());\n";2540    OS << "    if (DP.isMatch())\n";2541    OS << "      return MCTargetAsmParser::Match_Success;\n";2542    if (!CI.DiagnosticType.empty()) {2543      OS << "    if (DP.isNearMatch())\n";2544      OS << "      return " << Info.Target.getName() << "AsmParser::Match_"2545         << CI.DiagnosticType << ";\n";2546      OS << "    break;\n";2547    } else {2548      OS << "    break;\n";2549    }2550    OS << "  }\n";2551  }2552  OS << "  } // end switch (Kind)\n\n";2553 2554  const CodeGenRegBank &RegBank = Target.getRegBank();2555  ArrayRef<const Record *> RegClassesByHwMode = Target.getAllRegClassByHwMode();2556  unsigned NumClassesByHwMode = RegClassesByHwMode.size();2557 2558  if (!RegClassesByHwMode.empty()) {2559    OS << "  if (Operand.isReg() && Kind > MCK_LAST_REGISTER &&"2560          " Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {\n";2561 2562    const CodeGenHwModes &CGH = Target.getHwModes();2563    unsigned NumModes = CGH.getNumModeIds();2564 2565    OS << indent(4)2566       << "static constexpr MatchClassKind RegClassByHwModeMatchTable["2567       << NumModes << "][" << RegClassesByHwMode.size() << "] = {\n";2568 2569    // TODO: If the instruction predicates can statically resolve which hwmode,2570    // directly match the register class2571    for (unsigned M = 0; M < NumModes; ++M) {2572      OS << indent(6) << "{ // " << CGH.getModeName(M, /*IncludeDefault=*/true)2573         << '\n';2574      for (unsigned I = 0; I != NumClassesByHwMode; ++I) {2575        const Record *Class = RegClassesByHwMode[I];2576        const HwModeSelect &ModeSelect = CGH.getHwModeSelect(Class);2577 2578        auto FoundMode =2579            find_if(ModeSelect.Items, [=](const HwModeSelect::PairType P) {2580              return P.first == M;2581            });2582 2583        if (FoundMode == ModeSelect.Items.end()) {2584          OS << indent(8) << "InvalidMatchClass, // Missing mode\n";2585        } else {2586          const CodeGenRegisterClass *RegClass =2587              RegBank.getRegClass(FoundMode->second);2588          const ClassInfo *CI =2589              Info.RegisterClassClasses.at(RegClass->getDef());2590          OS << indent(8) << CI->Name << ",\n";2591        }2592      }2593 2594      OS << indent(6) << "},\n";2595    }2596 2597    OS << indent(4) << "};\n\n";2598 2599    OS << indent(4)2600       << "static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == "2601       << NumClassesByHwMode << ");\n";2602 2603    OS << indent(4)2604       << "const unsigned HwMode = "2605          "STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);\n"2606          "Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER "2607          "+ 1)];\n"2608          "  }\n\n";2609  }2610 2611  // Check for register operands, including sub-classes.2612  const auto &Regs = RegBank.getRegisters();2613  StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");2614  SmallVector<StringRef> Table(1 + Regs.size(), "InvalidMatchClass");2615  for (const auto &RC : Info.RegisterClasses) {2616    const auto &Reg = Target.getRegBank().getReg(RC.first);2617    Table[Reg->EnumValue] = RC.second->Name;2618  }2619  OS << "  if (Operand.isReg()) {\n";2620  OS << "    static constexpr uint16_t Table[" << Namespace2621     << "::NUM_TARGET_REGS] = {\n";2622  for (auto &MatchClassName : Table)2623    OS << "      " << MatchClassName << ",\n";2624  OS << "    };\n\n";2625  OS << "    MCRegister Reg = Operand.getReg();\n";2626  OS << "    MatchClassKind OpKind = Reg.isPhysical() ? "2627        "(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";2628  OS << "    return isSubclass(OpKind, Kind) ? "2629     << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "2630     << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";2631 2632  // Expected operand is a register, but actual is not.2633  OS << "  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";2634  OS << "    return getDiagKindFromRegisterClass(Kind);\n\n";2635 2636  // Generic fallthrough match failure case for operands that don't have2637  // specialized diagnostic types.2638  OS << "  return MCTargetAsmParser::Match_InvalidOperand;\n";2639  OS << "}\n\n";2640}2641 2642/// emitIsSubclass - Emit the subclass predicate function.2643static void emitIsSubclass(CodeGenTarget &Target,2644                           std::forward_list<ClassInfo> &Infos,2645                           raw_ostream &OS) {2646  OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";2647  OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";2648  OS << "  if (A == B)\n";2649  OS << "    return true;\n\n";2650 2651  // TODO: Use something like SequenceToOffsetTable to allow sequences to2652  // overlap in this table.2653  SmallVector<bool> SuperClassData;2654 2655  OS << "  [[maybe_unused]] static constexpr struct {\n";2656  OS << "    uint32_t Offset;\n";2657  OS << "    uint16_t Start;\n";2658  OS << "    uint16_t Length;\n";2659  OS << "  } Table[] = {\n";2660  OS << "    {0, 0, 0},\n"; // InvalidMatchClass2661  OS << "    {0, 0, 0},\n"; // OptionalMatchClass2662  for (const auto &A : Infos) {2663    SmallVector<bool> SuperClasses;2664    SuperClasses.push_back(false);        // InvalidMatchClass2665    SuperClasses.push_back(A.IsOptional); // OptionalMatchClass2666    for (const auto &B : Infos)2667      SuperClasses.push_back(&A != &B && A.isSubsetOf(B));2668 2669    // Trim leading and trailing zeros.2670    auto End = find_if(reverse(SuperClasses), [](bool B) { return B; }).base();2671    auto Start =2672        std::find_if(SuperClasses.begin(), End, [](bool B) { return B; });2673 2674    unsigned Offset = SuperClassData.size();2675    SuperClassData.append(Start, End);2676 2677    OS << "    {" << Offset << ", " << (Start - SuperClasses.begin()) << ", "2678       << (End - Start) << "},\n";2679  }2680  OS << "  };\n\n";2681 2682  if (SuperClassData.empty()) {2683    OS << "  return false;\n";2684  } else {2685    // Dump the boolean data packed into bytes.2686    SuperClassData.append(-SuperClassData.size() % 8, false);2687    OS << "  static constexpr uint8_t Data[] = {\n";2688    for (unsigned I = 0, E = SuperClassData.size(); I < E; I += 8) {2689      unsigned Byte = 0;2690      for (unsigned J = 0; J < 8; ++J)2691        Byte |= (unsigned)SuperClassData[I + J] << J;2692      OS << formatv("    {:X2},\n", Byte);2693    }2694    OS << "  };\n\n";2695 2696    OS << "  auto &Entry = Table[A];\n";2697    OS << "  unsigned Idx = B - Entry.Start;\n";2698    OS << "  if (Idx >= Entry.Length)\n";2699    OS << "    return false;\n";2700    OS << "  Idx += Entry.Offset;\n";2701    OS << "  return (Data[Idx / 8] >> (Idx % 8)) & 1;\n";2702  }2703  OS << "}\n\n";2704}2705 2706/// emitMatchTokenString - Emit the function to match a token string to the2707/// appropriate match class value.2708static void emitMatchTokenString(CodeGenTarget &Target,2709                                 std::forward_list<ClassInfo> &Infos,2710                                 raw_ostream &OS) {2711  // Construct the match list.2712  std::vector<StringMatcher::StringPair> Matches;2713  for (const auto &CI : Infos) {2714    if (CI.Kind == ClassInfo::Token)2715      Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");2716  }2717 2718  OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";2719 2720  StringMatcher("Name", Matches, OS).Emit();2721 2722  OS << "  return InvalidMatchClass;\n";2723  OS << "}\n\n";2724}2725 2726/// emitMatchRegisterName - Emit the function to match a string to the target2727/// specific register enum.2728static void emitMatchRegisterName(const CodeGenTarget &Target,2729                                  const Record *AsmParser, raw_ostream &OS) {2730  // Construct the match list.2731  std::vector<StringMatcher::StringPair> Matches;2732  const auto &Regs = Target.getRegBank().getRegisters();2733  std::string Namespace =2734      Regs.front().TheDef->getValueAsString("Namespace").str();2735  for (const CodeGenRegister &Reg : Regs) {2736    StringRef AsmName = Reg.TheDef->getValueAsString("AsmName");2737    if (AsmName.empty())2738      continue;2739 2740    Matches.emplace_back(AsmName.str(), "return " + Namespace +2741                                            "::" + Reg.getName().str() + ';');2742  }2743 2744  OS << "static MCRegister MatchRegisterName(StringRef Name) {\n";2745 2746  bool IgnoreDuplicates =2747      AsmParser->getValueAsBit("AllowDuplicateRegisterNames");2748  StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);2749 2750  OS << "  return " << Namespace << "::NoRegister;\n";2751  OS << "}\n\n";2752}2753 2754/// Emit the function to match a string to the target2755/// specific register enum.2756static void emitMatchRegisterAltName(const CodeGenTarget &Target,2757                                     const Record *AsmParser, raw_ostream &OS) {2758  // Construct the match list.2759  std::vector<StringMatcher::StringPair> Matches;2760  const auto &Regs = Target.getRegBank().getRegisters();2761  std::string Namespace =2762      Regs.front().TheDef->getValueAsString("Namespace").str();2763  for (const CodeGenRegister &Reg : Regs) {2764    for (StringRef AltName : Reg.TheDef->getValueAsListOfStrings("AltNames")) {2765      AltName = AltName.trim();2766 2767      // don't handle empty alternative names2768      if (AltName.empty())2769        continue;2770 2771      Matches.emplace_back(AltName.str(), "return " + Namespace +2772                                              "::" + Reg.getName().str() + ';');2773    }2774  }2775 2776  OS << "static MCRegister MatchRegisterAltName(StringRef Name) {\n";2777 2778  bool IgnoreDuplicates =2779      AsmParser->getValueAsBit("AllowDuplicateRegisterNames");2780  StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);2781 2782  OS << "  return " << Namespace << "::NoRegister;\n";2783  OS << "}\n\n";2784}2785 2786/// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.2787static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {2788  // Get the set of diagnostic types from all of the operand classes.2789  std::set<StringRef> Types;2790  for (const auto &OpClassEntry : Info.AsmOperandClasses) {2791    if (!OpClassEntry.second->DiagnosticType.empty())2792      Types.insert(OpClassEntry.second->DiagnosticType);2793  }2794  for (const auto &OpClassEntry : Info.RegisterClassClasses) {2795    if (!OpClassEntry.second->DiagnosticType.empty())2796      Types.insert(OpClassEntry.second->DiagnosticType);2797  }2798 2799  if (Types.empty())2800    return;2801 2802  // Now emit the enum entries.2803  for (StringRef Type : Types)2804    OS << "  Match_" << Type << ",\n";2805  OS << "  END_OPERAND_DIAGNOSTIC_TYPES\n";2806}2807 2808/// emitGetSubtargetFeatureName - Emit the helper function to get the2809/// user-level name for a subtarget feature.2810static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {2811  OS << "// User-level names for subtarget features that participate in\n"2812     << "// instruction matching.\n"2813     << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";2814  if (!Info.SubtargetFeatures.empty()) {2815    OS << "  switch(Val) {\n";2816    for (const SubtargetFeatureInfo &SFI :2817         make_second_range(Info.SubtargetFeatures)) {2818      // FIXME: Totally just a placeholder name to get the algorithm working.2819      OS << "  case " << SFI.getEnumBitName() << ": return \""2820         << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";2821    }2822    OS << "  default: return \"(unknown)\";\n";2823    OS << "  }\n";2824  } else {2825    // Nothing to emit, so skip the switch2826    OS << "  return \"(unknown)\";\n";2827  }2828  OS << "}\n\n";2829}2830 2831static std::string GetAliasRequiredFeatures(const Record *R,2832                                            const AsmMatcherInfo &Info) {2833  std::string Result;2834 2835  ListSeparator LS(" && ");2836  for (const Record *RF : R->getValueAsListOfDefs("Predicates")) {2837    const SubtargetFeatureInfo *F = Info.getSubtargetFeature(RF);2838    if (!F)2839      PrintFatalError(R->getLoc(),2840                      "Predicate '" + RF->getName() +2841                          "' is not marked as an AssemblerPredicate!");2842    Result += LS;2843    Result += "Features.test(" + F->getEnumBitName() + ')';2844  }2845 2846  return Result;2847}2848 2849static void2850emitMnemonicAliasVariant(raw_ostream &OS, const AsmMatcherInfo &Info,2851                         ArrayRef<const Record *> Aliases, unsigned Indent = 0,2852                         StringRef AsmParserVariantName = StringRef()) {2853  // Keep track of all the aliases from a mnemonic.  Use an std::map so that the2854  // iteration order of the map is stable.2855  std::map<std::string, std::vector<const Record *>> AliasesFromMnemonic;2856 2857  for (const Record *R : Aliases) {2858    // FIXME: Allow AssemblerVariantName to be a comma separated list.2859    StringRef AsmVariantName = R->getValueAsString("AsmVariantName");2860    if (AsmVariantName != AsmParserVariantName)2861      continue;2862    AliasesFromMnemonic[R->getValueAsString("FromMnemonic").lower()].push_back(2863        R);2864  }2865  if (AliasesFromMnemonic.empty())2866    return;2867 2868  // Process each alias a "from" mnemonic at a time, building the code executed2869  // by the string remapper.2870  std::vector<StringMatcher::StringPair> Cases;2871  for (const auto &AliasEntry : AliasesFromMnemonic) {2872    // Loop through each alias and emit code that handles each case.  If there2873    // are two instructions without predicates, emit an error.  If there is one,2874    // emit it last.2875    std::string MatchCode;2876    int AliasWithNoPredicate = -1;2877 2878    ArrayRef<const Record *> ToVec = AliasEntry.second;2879    for (const auto &[Idx, R] : enumerate(ToVec)) {2880      std::string FeatureMask = GetAliasRequiredFeatures(R, Info);2881 2882      // If this unconditionally matches, remember it for later and diagnose2883      // duplicates.2884      if (FeatureMask.empty()) {2885        if (AliasWithNoPredicate != -1 &&2886            R->getValueAsString("ToMnemonic") !=2887                ToVec[AliasWithNoPredicate]->getValueAsString("ToMnemonic")) {2888          // We can't have two different aliases from the same mnemonic with no2889          // predicate.2890          PrintError(2891              ToVec[AliasWithNoPredicate]->getLoc(),2892              "two different MnemonicAliases with the same 'from' mnemonic!");2893          PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");2894        }2895 2896        AliasWithNoPredicate = Idx;2897        continue;2898      }2899      if (R->getValueAsString("ToMnemonic") == AliasEntry.first)2900        PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");2901 2902      if (!MatchCode.empty())2903        MatchCode += "else ";2904      MatchCode += "if (" + FeatureMask + ")\n";2905      MatchCode += "  Mnemonic = \"";2906      MatchCode += R->getValueAsString("ToMnemonic").lower();2907      MatchCode += "\";\n";2908    }2909 2910    if (AliasWithNoPredicate != -1) {2911      const Record *R = ToVec[AliasWithNoPredicate];2912      if (!MatchCode.empty())2913        MatchCode += "else\n  ";2914      MatchCode += "Mnemonic = \"";2915      MatchCode += R->getValueAsString("ToMnemonic").lower();2916      MatchCode += "\";\n";2917    }2918 2919    MatchCode += "return;";2920 2921    Cases.emplace_back(AliasEntry.first, MatchCode);2922  }2923  StringMatcher("Mnemonic", Cases, OS).Emit(Indent);2924}2925 2926/// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,2927/// emit a function for them and return true, otherwise return false.2928static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,2929                                CodeGenTarget &Target) {2930  // Ignore aliases when match-prefix is set.2931  if (!MatchPrefix.empty())2932    return false;2933 2934  ArrayRef<const Record *> Aliases =2935      Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");2936  if (Aliases.empty())2937    return false;2938 2939  OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "2940        "const FeatureBitset &Features, unsigned VariantID) {\n";2941  unsigned VariantCount = Target.getAsmParserVariantCount();2942  for (unsigned VC = 0; VC != VariantCount; ++VC) {2943    const Record *AsmVariant = Target.getAsmParserVariant(VC);2944    int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");2945    StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name");2946 2947    // If the variant doesn't have a name, defer to the emitMnemonicAliasVariant2948    // call after the loop.2949    if (AsmParserVariantName.empty()) {2950      assert(VariantCount == 1 && "Multiple variants should each be named");2951      continue;2952    }2953 2954    if (VC == 0)2955      OS << "  switch (VariantID) {\n";2956    OS << "  case " << AsmParserVariantNo << ":\n";2957    emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,2958                             AsmParserVariantName);2959    OS << "    break;\n";2960 2961    if (VC == VariantCount - 1)2962      OS << "  }\n";2963  }2964 2965  // Emit aliases that apply to all variants.2966  emitMnemonicAliasVariant(OS, Info, Aliases);2967 2968  OS << "}\n\n";2969 2970  return true;2971}2972 2973static void2974emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,2975                         const AsmMatcherInfo &Info, StringRef ClassName,2976                         const StringToOffsetTable &StringTable,2977                         unsigned MaxMnemonicIndex, unsigned MaxFeaturesIndex,2978                         bool HasMnemonicFirst, const Record &AsmParser) {2979  unsigned MaxMask = 0;2980  for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {2981    MaxMask |= OMI.OperandMask;2982  }2983 2984  // Emit the static custom operand parsing table;2985  OS << "namespace {\n";2986  OS << "  struct OperandMatchEntry {\n";2987  OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex) << " Mnemonic;\n";2988  OS << "    " << getMinimalTypeForRange(MaxMask) << " OperandMask;\n";2989  OS << "    "2990     << getMinimalTypeForRange(2991            std::distance(Info.Classes.begin(), Info.Classes.end()) +2992            2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)2993     << " Class;\n";2994  OS << "    " << getMinimalTypeForRange(MaxFeaturesIndex)2995     << " RequiredFeaturesIdx;\n\n";2996  OS << "    StringRef getMnemonic() const {\n";2997  OS << "      return StringRef(MnemonicTable + Mnemonic + 1,\n";2998  OS << "                       MnemonicTable[Mnemonic]);\n";2999  OS << "    }\n";3000  OS << "  };\n\n";3001 3002  OS << "  // Predicate for searching for an opcode.\n";3003  OS << "  struct LessOpcodeOperand {\n";3004  OS << "    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";3005  OS << "      return LHS.getMnemonic()  < RHS;\n";3006  OS << "    }\n";3007  OS << "    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";3008  OS << "      return LHS < RHS.getMnemonic();\n";3009  OS << "    }\n";3010  OS << "    bool operator()(const OperandMatchEntry &LHS,";3011  OS << " const OperandMatchEntry &RHS) {\n";3012  OS << "      return LHS.getMnemonic() < RHS.getMnemonic();\n";3013  OS << "    }\n";3014  OS << "  };\n";3015 3016  OS << "} // end anonymous namespace\n\n";3017 3018  OS << "static const OperandMatchEntry OperandMatchTable["3019     << Info.OperandMatchInfo.size() << "] = {\n";3020 3021  OS << "  /* Operand List Mnemonic, Mask, Operand Class, Features */\n";3022  for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {3023    const MatchableInfo &II = *OMI.MI;3024 3025    OS << "  { ";3026 3027    // Store a pascal-style length byte in the mnemonic.3028    std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower();3029    OS << *StringTable.GetStringOffset(LenMnemonic) << " /* " << II.Mnemonic3030       << " */, ";3031 3032    OS << OMI.OperandMask;3033    OS << " /* ";3034    ListSeparator LS;3035    for (int i = 0, e = 31; i != e; ++i)3036      if (OMI.OperandMask & (1 << i))3037        OS << LS << i;3038    OS << " */, ";3039 3040    OS << OMI.CI->Name;3041 3042    // Write the required features mask.3043    OS << ", AMFBS";3044    if (II.RequiredFeatures.empty())3045      OS << "_None";3046    else3047      for (const auto &F : II.RequiredFeatures)3048        OS << '_' << F->TheDef->getName();3049 3050    OS << " },\n";3051  }3052  OS << "};\n\n";3053 3054  // Emit the operand class switch to call the correct custom parser for3055  // the found operand class.3056  OS << "ParseStatus " << Target.getName() << ClassName << "::\n"3057     << "tryCustomParseOperand(OperandVector"3058     << " &Operands,\n                      unsigned MCK) {\n\n"3059     << "  switch(MCK) {\n";3060 3061  for (const auto &CI : Info.Classes) {3062    if (CI.ParserMethod.empty())3063      continue;3064    OS << "  case " << CI.Name << ":\n"3065       << "    return " << CI.ParserMethod << "(Operands);\n";3066  }3067 3068  OS << "  default:\n";3069  OS << "    return ParseStatus::NoMatch;\n";3070  OS << "  }\n";3071  OS << "  return ParseStatus::NoMatch;\n";3072  OS << "}\n\n";3073 3074  // Emit the static custom operand parser. This code is very similar with3075  // the other matcher. Also use MatchResultTy here just in case we go for3076  // a better error handling.3077  OS << "ParseStatus " << Target.getName() << ClassName << "::\n"3078     << "MatchOperandParserImpl(OperandVector"3079     << " &Operands,\n                       StringRef Mnemonic,\n"3080     << "                       bool ParseForAllFeatures) {\n";3081 3082  // Emit code to get the available features.3083  OS << "  // Get the current feature set.\n";3084  OS << "  const FeatureBitset &AvailableFeatures = "3085        "getAvailableFeatures();\n\n";3086 3087  OS << "  // Get the next operand index.\n";3088  OS << "  unsigned NextOpNum = Operands.size()"3089     << (HasMnemonicFirst ? " - 1" : "") << ";\n";3090 3091  // Emit code to search the table.3092  OS << "  // Search the table.\n";3093  if (HasMnemonicFirst) {3094    OS << "  auto MnemonicRange =\n";3095    OS << "    std::equal_range(std::begin(OperandMatchTable), "3096          "std::end(OperandMatchTable),\n";3097    OS << "                     Mnemonic, LessOpcodeOperand());\n\n";3098  } else {3099    OS << "  auto MnemonicRange = std::pair(std::begin(OperandMatchTable),"3100          " std::end(OperandMatchTable));\n";3101    OS << "  if (!Mnemonic.empty())\n";3102    OS << "    MnemonicRange =\n";3103    OS << "      std::equal_range(std::begin(OperandMatchTable), "3104          "std::end(OperandMatchTable),\n";3105    OS << "                       Mnemonic, LessOpcodeOperand());\n\n";3106  }3107 3108  OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";3109  OS << "    return ParseStatus::NoMatch;\n\n";3110 3111  OS << "  for (const OperandMatchEntry *it = MnemonicRange.first,\n"3112     << "       *ie = MnemonicRange.second; it != ie; ++it) {\n";3113 3114  OS << "    // equal_range guarantees that instruction mnemonic matches.\n";3115  OS << "    assert(Mnemonic == it->getMnemonic());\n\n";3116 3117  // Emit check that the required features are available.3118  OS << "    // check if the available features match\n";3119  OS << "    const FeatureBitset &RequiredFeatures = "3120        "FeatureBitsets[it->RequiredFeaturesIdx];\n";3121  OS << "    if (!ParseForAllFeatures && (AvailableFeatures & "3122        "RequiredFeatures) != RequiredFeatures)\n";3123  OS << "      continue;\n\n";3124 3125  // Emit check to ensure the operand number matches.3126  OS << "    // check if the operand in question has a custom parser.\n";3127  OS << "    if (!(it->OperandMask & (1 << NextOpNum)))\n";3128  OS << "      continue;\n\n";3129 3130  // Emit call to the custom parser method3131  StringRef ParserName = AsmParser.getValueAsString("OperandParserMethod");3132  if (ParserName.empty())3133    ParserName = "tryCustomParseOperand";3134  OS << "    // call custom parse method to handle the operand\n";3135  OS << "    ParseStatus Result = " << ParserName << "(Operands, it->Class);\n";3136  OS << "    if (!Result.isNoMatch())\n";3137  OS << "      return Result;\n";3138  OS << "  }\n\n";3139 3140  OS << "  // Okay, we had no match.\n";3141  OS << "  return ParseStatus::NoMatch;\n";3142  OS << "}\n\n";3143}3144 3145static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,3146                                          AsmMatcherInfo &Info, raw_ostream &OS,3147                                          bool HasOptionalOperands) {3148  std::string AsmParserName =3149      Info.AsmParser->getValueAsString("AsmParserClassName").str();3150  OS << "static bool ";3151  OS << "checkAsmTiedOperandConstraints(const " << Target.getName()3152     << AsmParserName << "&AsmParser,\n";3153  OS << "                               unsigned Kind, const OperandVector "3154        "&Operands,\n";3155  if (HasOptionalOperands)3156    OS << "                               ArrayRef<unsigned> DefaultsOffset,\n";3157  OS << "                               uint64_t &ErrorInfo) {\n";3158  OS << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";3159  OS << "  const uint8_t *Converter = ConversionTable[Kind];\n";3160  OS << "  for (const uint8_t *p = Converter; *p; p += 2) {\n";3161  OS << "    switch (*p) {\n";3162  OS << "    case CVT_Tied: {\n";3163  OS << "      unsigned OpIdx = *(p + 1);\n";3164  OS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";3165  OS << "                              std::begin(TiedAsmOperandTable)) &&\n";3166  OS << "             \"Tied operand not found\");\n";3167  OS << "      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";3168  OS << "      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";3169  if (HasOptionalOperands) {3170    // When optional operands are involved, formal and actual operand indices3171    // may differ. Map the former to the latter by subtracting the number of3172    // absent optional operands.3173    OS << "      OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];\n";3174    OS << "      OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];\n";3175  }3176  OS << "      if (OpndNum1 != OpndNum2) {\n";3177  OS << "        auto &SrcOp1 = Operands[OpndNum1];\n";3178  OS << "        auto &SrcOp2 = Operands[OpndNum2];\n";3179  OS << "        if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {\n";3180  OS << "          ErrorInfo = OpndNum2;\n";3181  OS << "          return false;\n";3182  OS << "        }\n";3183  OS << "      }\n";3184  OS << "      break;\n";3185  OS << "    }\n";3186  OS << "    default:\n";3187  OS << "      break;\n";3188  OS << "    }\n";3189  OS << "  }\n";3190  OS << "  return true;\n";3191  OS << "}\n\n";3192}3193 3194static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,3195                                     unsigned VariantCount) {3196  OS << "static std::string " << Target.getName()3197     << "MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,"3198     << " unsigned VariantID) {\n";3199  if (!VariantCount)3200    OS << "  return \"\";";3201  else {3202    OS << "  const unsigned MaxEditDist = 2;\n";3203    OS << "  std::vector<StringRef> Candidates;\n";3204    OS << "  StringRef Prev = \"\";\n\n";3205 3206    OS << "  // Find the appropriate table for this asm variant.\n";3207    OS << "  const MatchEntry *Start, *End;\n";3208    OS << "  switch (VariantID) {\n";3209    OS << "  default: llvm_unreachable(\"invalid variant!\");\n";3210    for (unsigned VC = 0; VC != VariantCount; ++VC) {3211      const Record *AsmVariant = Target.getAsmParserVariant(VC);3212      int AsmVariantNo = AsmVariant->getValueAsInt("Variant");3213      OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC3214         << "); End = std::end(MatchTable" << VC << "); break;\n";3215    }3216    OS << "  }\n\n";3217    OS << "  for (auto I = Start; I < End; I++) {\n";3218    OS << "    // Ignore unsupported instructions.\n";3219    OS << "    const FeatureBitset &RequiredFeatures = "3220          "FeatureBitsets[I->RequiredFeaturesIdx];\n";3221    OS << "    if ((FBS & RequiredFeatures) != RequiredFeatures)\n";3222    OS << "      continue;\n";3223    OS << "\n";3224    OS << "    StringRef T = I->getMnemonic();\n";3225    OS << "    // Avoid recomputing the edit distance for the same string.\n";3226    OS << "    if (T == Prev)\n";3227    OS << "      continue;\n";3228    OS << "\n";3229    OS << "    Prev = T;\n";3230    OS << "    unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";3231    OS << "    if (Dist <= MaxEditDist)\n";3232    OS << "      Candidates.push_back(T);\n";3233    OS << "  }\n";3234    OS << "\n";3235    OS << "  if (Candidates.empty())\n";3236    OS << "    return \"\";\n";3237    OS << "\n";3238    OS << "  std::string Res = \", did you mean: \";\n";3239    OS << "  unsigned i = 0;\n";3240    OS << "  for (; i < Candidates.size() - 1; i++)\n";3241    OS << "    Res += Candidates[i].str() + \", \";\n";3242    OS << "  return Res + Candidates[i].str() + \"?\";\n";3243  }3244  OS << "}\n";3245  OS << "\n";3246}3247 3248static void emitMnemonicChecker(raw_ostream &OS, CodeGenTarget &Target,3249                                unsigned VariantCount, bool HasMnemonicFirst,3250                                bool HasMnemonicAliases) {3251  OS << "static bool " << Target.getName()3252     << "CheckMnemonic(StringRef Mnemonic,\n";3253  OS << "                                "3254     << "const FeatureBitset &AvailableFeatures,\n";3255  OS << "                                "3256     << "unsigned VariantID) {\n";3257 3258  if (!VariantCount) {3259    OS << "  return false;\n";3260  } else {3261    if (HasMnemonicAliases) {3262      OS << "  // Process all MnemonicAliases to remap the mnemonic.\n";3263      OS << "  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);";3264      OS << "\n\n";3265    }3266    OS << "  // Find the appropriate table for this asm variant.\n";3267    OS << "  const MatchEntry *Start, *End;\n";3268    OS << "  switch (VariantID) {\n";3269    OS << "  default: llvm_unreachable(\"invalid variant!\");\n";3270    for (unsigned VC = 0; VC != VariantCount; ++VC) {3271      const Record *AsmVariant = Target.getAsmParserVariant(VC);3272      int AsmVariantNo = AsmVariant->getValueAsInt("Variant");3273      OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC3274         << "); End = std::end(MatchTable" << VC << "); break;\n";3275    }3276    OS << "  }\n\n";3277 3278    OS << "  // Search the table.\n";3279    if (HasMnemonicFirst) {3280      OS << "  auto MnemonicRange = "3281            "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";3282    } else {3283      OS << "  auto MnemonicRange = std::pair(Start, End);\n";3284      OS << "  unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";3285      OS << "  if (!Mnemonic.empty())\n";3286      OS << "    MnemonicRange = "3287         << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";3288    }3289 3290    OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";3291    OS << "    return false;\n\n";3292 3293    OS << "  for (const MatchEntry *it = MnemonicRange.first, "3294       << "*ie = MnemonicRange.second;\n";3295    OS << "       it != ie; ++it) {\n";3296    OS << "    const FeatureBitset &RequiredFeatures =\n";3297    OS << "      FeatureBitsets[it->RequiredFeaturesIdx];\n";3298    OS << "    if ((AvailableFeatures & RequiredFeatures) == ";3299    OS << "RequiredFeatures)\n";3300    OS << "      return true;\n";3301    OS << "  }\n";3302    OS << "  return false;\n";3303  }3304  OS << "}\n";3305  OS << "\n";3306}3307 3308// Emit a function mapping match classes to strings, for debugging.3309static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,3310                                    raw_ostream &OS) {3311  OS << "#ifndef NDEBUG\n";3312  OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";3313  OS << "  switch (Kind) {\n";3314 3315  OS << "  case InvalidMatchClass: return \"InvalidMatchClass\";\n";3316  OS << "  case OptionalMatchClass: return \"OptionalMatchClass\";\n";3317  for (const auto &CI : Infos) {3318    OS << "  case " << CI.Name << ": return \"" << CI.Name << "\";\n";3319  }3320  OS << "  case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";3321 3322  OS << "  }\n";3323  OS << "  llvm_unreachable(\"unhandled MatchClassKind!\");\n";3324  OS << "}\n\n";3325  OS << "#endif // NDEBUG\n";3326}3327 3328static std::string3329getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {3330  std::string Name = "AMFBS";3331  for (const Record *Feature : FeatureBitset)3332    Name += ("_" + Feature->getName()).str();3333  return Name;3334}3335 3336void AsmMatcherEmitter::run(raw_ostream &OS) {3337  CodeGenTarget Target(Records);3338  const Record *AsmParser = Target.getAsmParser();3339  StringRef ClassName = AsmParser->getValueAsString("AsmParserClassName");3340 3341  emitSourceFileHeader("Assembly Matcher Source Fragment", OS, Records);3342 3343  // Compute the information on the instructions to match.3344  AsmMatcherInfo Info(AsmParser, Target, Records);3345  Info.buildInfo();3346 3347  bool PreferSmallerInstructions = getPreferSmallerInstructions(Target);3348  // Sort the instruction table using the partial order on classes. We use3349  // stable_sort to ensure that ambiguous instructions are still3350  // deterministically ordered.3351  llvm::stable_sort(3352      Info.Matchables,3353      [PreferSmallerInstructions](const std::unique_ptr<MatchableInfo> &A,3354                                  const std::unique_ptr<MatchableInfo> &B) {3355        return A->shouldBeMatchedBefore(*B, PreferSmallerInstructions);3356      });3357 3358#ifdef EXPENSIVE_CHECKS3359  // Verify that the table is sorted and operator < works transitively.3360  for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;3361       ++I) {3362    for (auto J = I; J != E; ++J) {3363      assert(!(*J)->shouldBeMatchedBefore(**I, PreferSmallerInstructions));3364    }3365  }3366#endif3367 3368  DEBUG_WITH_TYPE("instruction_info", {3369    for (const auto &MI : Info.Matchables)3370      MI->dump();3371  });3372 3373  // Check for ambiguous matchables.3374  DEBUG_WITH_TYPE("ambiguous_instrs", {3375    unsigned NumAmbiguous = 0;3376    for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;3377         ++I) {3378      for (auto J = std::next(I); J != E; ++J) {3379        const MatchableInfo &A = **I;3380        const MatchableInfo &B = **J;3381 3382        if (A.couldMatchAmbiguouslyWith(B, PreferSmallerInstructions)) {3383          errs() << "warning: ambiguous matchables:\n";3384          A.dump();3385          errs() << "\nis incomparable with:\n";3386          B.dump();3387          errs() << "\n\n";3388          ++NumAmbiguous;3389        }3390      }3391    }3392    if (NumAmbiguous)3393      errs() << "warning: " << NumAmbiguous << " ambiguous matchables!\n";3394  });3395 3396  // Compute the information on the custom operand parsing.3397  Info.buildOperandMatchInfo();3398 3399  bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");3400  bool HasOptionalOperands = Info.hasOptionalOperands();3401  bool ReportMultipleNearMisses =3402      AsmParser->getValueAsBit("ReportMultipleNearMisses");3403 3404  // Write the output.3405 3406  // Information for the class declaration.3407  OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";3408  OS << "#undef GET_ASSEMBLER_HEADER\n";3409  OS << "  // This should be included into the middle of the declaration of\n";3410  OS << "  // your subclasses implementation of MCTargetAsmParser.\n";3411  OS << "  FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) "3412        "const;\n";3413  if (HasOptionalOperands) {3414    OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "3415       << "unsigned Opcode,\n"3416       << "                       const OperandVector &Operands,\n"3417       << "                       const SmallBitVector "3418          "&OptionalOperandsMask,\n"3419       << "                       ArrayRef<unsigned> DefaultsOffset);\n";3420  } else {3421    OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "3422       << "unsigned Opcode,\n"3423       << "                       const OperandVector &Operands);\n";3424  }3425  OS << "  void convertToMapAndConstraints(unsigned Kind,\n                ";3426  OS << "           const OperandVector &Operands) override;\n";3427  OS << "  unsigned MatchInstructionImpl(const OperandVector &Operands,\n"3428     << "                                MCInst &Inst,\n";3429  if (ReportMultipleNearMisses)3430    OS << "                                SmallVectorImpl<NearMissInfo> "3431          "*NearMisses,\n";3432  else3433    OS << "                                uint64_t &ErrorInfo,\n"3434       << "                                FeatureBitset &MissingFeatures,\n";3435  OS << "                                bool matchingInlineAsm,\n"3436     << "                                unsigned VariantID = 0);\n";3437  if (!ReportMultipleNearMisses)3438    OS << "  unsigned MatchInstructionImpl(const OperandVector &Operands,\n"3439       << "                                MCInst &Inst,\n"3440       << "                                uint64_t &ErrorInfo,\n"3441       << "                                bool matchingInlineAsm,\n"3442       << "                                unsigned VariantID = 0) {\n"3443       << "    FeatureBitset MissingFeatures;\n"3444       << "    return MatchInstructionImpl(Operands, Inst, ErrorInfo, "3445          "MissingFeatures,\n"3446       << "                                matchingInlineAsm, VariantID);\n"3447       << "  }\n\n";3448 3449  if (!Info.OperandMatchInfo.empty()) {3450    OS << "  ParseStatus MatchOperandParserImpl(\n";3451    OS << "    OperandVector &Operands,\n";3452    OS << "    StringRef Mnemonic,\n";3453    OS << "    bool ParseForAllFeatures = false);\n";3454 3455    OS << "  ParseStatus tryCustomParseOperand(\n";3456    OS << "    OperandVector &Operands,\n";3457    OS << "    unsigned MCK);\n\n";3458  }3459 3460  OS << "#endif // GET_ASSEMBLER_HEADER\n\n";3461 3462  // Emit the operand match diagnostic enum names.3463  OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";3464  OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";3465  emitOperandDiagnosticTypes(Info, OS);3466  OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";3467 3468  OS << "\n#ifdef GET_REGISTER_MATCHER\n";3469  OS << "#undef GET_REGISTER_MATCHER\n\n";3470 3471  // Emit the subtarget feature enumeration.3472  SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(3473      Info.SubtargetFeatures, OS);3474 3475  // Emit the function to match a register name to number.3476  // This should be omitted for Mips target3477  if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))3478    emitMatchRegisterName(Target, AsmParser, OS);3479 3480  if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))3481    emitMatchRegisterAltName(Target, AsmParser, OS);3482 3483  OS << "#endif // GET_REGISTER_MATCHER\n\n";3484 3485  OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";3486  OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";3487 3488  // Generate the helper function to get the names for subtarget features.3489  emitGetSubtargetFeatureName(Info, OS);3490 3491  OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";3492 3493  OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";3494  OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";3495 3496  // Generate the function that remaps for mnemonic aliases.3497  bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);3498 3499  // Generate the convertToMCInst function to convert operands into an MCInst.3500  // Also, generate the convertToMapAndConstraints function for MS-style inline3501  // assembly.  The latter doesn't actually generate a MCInst.3502  unsigned NumConverters =3503      emitConvertFuncs(Target, ClassName, Info.Matchables, HasMnemonicFirst,3504                       HasOptionalOperands, OS);3505 3506  // Emit the enumeration for classes which participate in matching.3507  emitMatchClassEnumeration(Target, Info.Classes, OS);3508 3509  // Emit a function to get the user-visible string to describe an operand3510  // match failure in diagnostics.3511  emitOperandMatchErrorDiagStrings(Info, OS);3512 3513  // Emit a function to map register classes to operand match failure codes.3514  emitRegisterMatchErrorFunc(Info, OS);3515 3516  // Emit the routine to match token strings to their match class.3517  emitMatchTokenString(Target, Info.Classes, OS);3518 3519  // Emit the subclass predicate routine.3520  emitIsSubclass(Target, Info.Classes, OS);3521 3522  // Emit the routine to validate an operand against a match class.3523  emitValidateOperandClass(Target, Info, OS);3524 3525  emitMatchClassKindNames(Info.Classes, OS);3526 3527  // Emit the available features compute function.3528  SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(3529      Info.Target.getName(), ClassName, "ComputeAvailableFeatures",3530      Info.SubtargetFeatures, OS);3531 3532  if (!ReportMultipleNearMisses)3533    emitAsmTiedOperandConstraints(Target, Info, OS, HasOptionalOperands);3534 3535  StringToOffsetTable StringTable(/*AppendZero=*/false);3536 3537  size_t MaxNumOperands = 0;3538  unsigned MaxMnemonicIndex = 0;3539  bool HasDeprecation = false;3540  for (const auto &MI : Info.Matchables) {3541    MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());3542    HasDeprecation |= MI->HasDeprecation;3543 3544    // Store a pascal-style length byte in the mnemonic.3545    std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower();3546    MaxMnemonicIndex = std::max(MaxMnemonicIndex,3547                                StringTable.GetOrAddStringOffset(LenMnemonic));3548  }3549 3550  OS << "static const char MnemonicTable[] =\n";3551  StringTable.EmitString(OS);3552  OS << ";\n\n";3553 3554  std::vector<std::vector<const Record *>> FeatureBitsets;3555  for (const auto &MI : Info.Matchables) {3556    if (MI->RequiredFeatures.empty())3557      continue;3558    FeatureBitsets.emplace_back();3559    for (const auto *F : MI->RequiredFeatures)3560      FeatureBitsets.back().push_back(F->TheDef);3561  }3562 3563  llvm::sort(FeatureBitsets,3564             [&](ArrayRef<const Record *> A, ArrayRef<const Record *> B) {3565               if (A.size() != B.size())3566                 return A.size() < B.size();3567               for (const auto [ARec, BRec] : zip_equal(A, B)) {3568                 if (ARec->getName() != BRec->getName())3569                   return ARec->getName() < BRec->getName();3570               }3571               return false;3572             });3573  FeatureBitsets.erase(llvm::unique(FeatureBitsets), FeatureBitsets.end());3574  OS << "// Feature bitsets.\n"3575     << "enum : " << getMinimalTypeForRange(FeatureBitsets.size()) << " {\n"3576     << "  AMFBS_None,\n";3577  for (const auto &FeatureBitset : FeatureBitsets) {3578    if (FeatureBitset.empty())3579      continue;3580    OS << "  " << getNameForFeatureBitset(FeatureBitset) << ",\n";3581  }3582  OS << "};\n\n"3583     << "static constexpr FeatureBitset FeatureBitsets[] = {\n"3584     << "  {}, // AMFBS_None\n";3585  for (const auto &FeatureBitset : FeatureBitsets) {3586    if (FeatureBitset.empty())3587      continue;3588    OS << "  {";3589    for (const auto &Feature : FeatureBitset) {3590      const auto &I = Info.SubtargetFeatures.find(Feature);3591      assert(I != Info.SubtargetFeatures.end() && "Didn't import predicate?");3592      OS << I->second.getEnumBitName() << ", ";3593    }3594    OS << "},\n";3595  }3596  OS << "};\n\n";3597 3598  // Emit the static match table; unused classes get initialized to 0 which is3599  // guaranteed to be InvalidMatchClass.3600  //3601  // FIXME: We can reduce the size of this table very easily. First, we change3602  // it so that store the kinds in separate bit-fields for each index, which3603  // only needs to be the max width used for classes at that index (we also need3604  // to reject based on this during classification). If we then make sure to3605  // order the match kinds appropriately (putting mnemonics last), then we3606  // should only end up using a few bits for each class, especially the ones3607  // following the mnemonic.3608  OS << "namespace {\n";3609  OS << "  struct MatchEntry {\n";3610  OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex) << " Mnemonic;\n";3611  OS << "    uint16_t Opcode;\n";3612  OS << "    " << getMinimalTypeForRange(NumConverters) << " ConvertFn;\n";3613  OS << "    " << getMinimalTypeForRange(FeatureBitsets.size())3614     << " RequiredFeaturesIdx;\n";3615  OS << "    "3616     << getMinimalTypeForRange(3617            std::distance(Info.Classes.begin(), Info.Classes.end()) +3618            2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)3619     << " Classes[" << MaxNumOperands << "];\n";3620  OS << "    StringRef getMnemonic() const {\n";3621  OS << "      return StringRef(MnemonicTable + Mnemonic + 1,\n";3622  OS << "                       MnemonicTable[Mnemonic]);\n";3623  OS << "    }\n";3624  OS << "  };\n\n";3625 3626  OS << "  // Predicate for searching for an opcode.\n";3627  OS << "  struct LessOpcode {\n";3628  OS << "    bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";3629  OS << "      return LHS.getMnemonic() < RHS;\n";3630  OS << "    }\n";3631  OS << "    bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";3632  OS << "      return LHS < RHS.getMnemonic();\n";3633  OS << "    }\n";3634  OS << "    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";3635  OS << "      return LHS.getMnemonic() < RHS.getMnemonic();\n";3636  OS << "    }\n";3637  OS << "  };\n";3638 3639  OS << "} // end anonymous namespace\n\n";3640 3641  unsigned VariantCount = Target.getAsmParserVariantCount();3642  for (unsigned VC = 0; VC != VariantCount; ++VC) {3643    const Record *AsmVariant = Target.getAsmParserVariant(VC);3644    int AsmVariantNo = AsmVariant->getValueAsInt("Variant");3645 3646    OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";3647 3648    for (const auto &MI : Info.Matchables) {3649      if (MI->AsmVariantID != AsmVariantNo)3650        continue;3651 3652      // Store a pascal-style length byte in the mnemonic.3653      std::string LenMnemonic =3654          char(MI->Mnemonic.size()) + MI->Mnemonic.lower();3655      OS << "  { " << *StringTable.GetStringOffset(LenMnemonic) << " /* "3656         << MI->Mnemonic << " */, " << Target.getInstNamespace()3657         << "::" << MI->getResultInst()->getName() << ", "3658         << MI->ConversionFnKind << ", ";3659 3660      // Write the required features mask.3661      OS << "AMFBS";3662      if (MI->RequiredFeatures.empty())3663        OS << "_None";3664      else3665        for (const auto &F : MI->RequiredFeatures)3666          OS << '_' << F->TheDef->getName();3667 3668      OS << ", { ";3669      ListSeparator LS;3670      for (const MatchableInfo::AsmOperand &Op : MI->AsmOperands)3671        OS << LS << Op.Class->Name;3672      OS << " }, },\n";3673    }3674 3675    OS << "};\n\n";3676  }3677 3678  OS << "#include \"llvm/Support/Debug.h\"\n";3679  OS << "#include \"llvm/Support/Format.h\"\n\n";3680 3681  // Finally, build the match function.3682  OS << "unsigned " << Target.getName() << ClassName << "::\n"3683     << "MatchInstructionImpl(const OperandVector &Operands,\n";3684  OS << "                     MCInst &Inst,\n";3685  if (ReportMultipleNearMisses)3686    OS << "                     SmallVectorImpl<NearMissInfo> *NearMisses,\n";3687  else3688    OS << "                     uint64_t &ErrorInfo,\n"3689       << "                     FeatureBitset &MissingFeatures,\n";3690  OS << "                     bool matchingInlineAsm, unsigned VariantID) {\n";3691 3692  if (!ReportMultipleNearMisses) {3693    OS << "  // Eliminate obvious mismatches.\n";3694    OS << "  if (Operands.size() > " << (MaxNumOperands + HasMnemonicFirst)3695       << ") {\n";3696    OS << "    ErrorInfo = " << (MaxNumOperands + HasMnemonicFirst) << ";\n";3697    OS << "    return Match_InvalidOperand;\n";3698    OS << "  }\n\n";3699  }3700 3701  // Emit code to get the available features.3702  OS << "  // Get the current feature set.\n";3703  OS << "  const FeatureBitset &AvailableFeatures = "3704        "getAvailableFeatures();\n\n";3705 3706  OS << "  // Get the instruction mnemonic, which is the first token.\n";3707  if (HasMnemonicFirst) {3708    OS << "  StringRef Mnemonic = ((" << Target.getName()3709       << "Operand &)*Operands[0]).getToken();\n\n";3710  } else {3711    OS << "  StringRef Mnemonic;\n";3712    OS << "  if (Operands[0]->isToken())\n";3713    OS << "    Mnemonic = ((" << Target.getName()3714       << "Operand &)*Operands[0]).getToken();\n\n";3715  }3716 3717  if (HasMnemonicAliases) {3718    OS << "  // Process all MnemonicAliases to remap the mnemonic.\n";3719    OS << "  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";3720  }3721 3722  // Emit code to compute the class list for this operand vector.3723  if (!ReportMultipleNearMisses) {3724    OS << "  // Some state to try to produce better error messages.\n";3725    OS << "  bool HadMatchOtherThanFeatures = false;\n";3726    OS << "  bool HadMatchOtherThanPredicate = false;\n";3727    OS << "  unsigned RetCode = Match_InvalidOperand;\n";3728    OS << "  MissingFeatures.set();\n";3729    OS << "  // Set ErrorInfo to the operand that mismatches if it is\n";3730    OS << "  // wrong for all instances of the instruction.\n";3731    OS << "  ErrorInfo = ~0ULL;\n";3732  }3733 3734  if (HasOptionalOperands)3735    OS << "  SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n";3736 3737  // Emit code to search the table.3738  OS << "  // Find the appropriate table for this asm variant.\n";3739  OS << "  const MatchEntry *Start, *End;\n";3740  OS << "  switch (VariantID) {\n";3741  OS << "  default: llvm_unreachable(\"invalid variant!\");\n";3742  for (unsigned VC = 0; VC != VariantCount; ++VC) {3743    const Record *AsmVariant = Target.getAsmParserVariant(VC);3744    int AsmVariantNo = AsmVariant->getValueAsInt("Variant");3745    OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC3746       << "); End = std::end(MatchTable" << VC << "); break;\n";3747  }3748  OS << "  }\n";3749 3750  OS << "  // Search the table.\n";3751  if (HasMnemonicFirst) {3752    OS << "  auto MnemonicRange = "3753          "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";3754  } else {3755    OS << "  auto MnemonicRange = std::pair(Start, End);\n";3756    OS << "  unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";3757    OS << "  if (!Mnemonic.empty())\n";3758    OS << "    MnemonicRange = "3759          "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";3760  }3761 3762  OS << "  DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" "3763        "<<\n"3764     << "  std::distance(MnemonicRange.first, MnemonicRange.second) <<\n"3765     << "  \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";3766 3767  OS << "  // Return a more specific error code if no mnemonics match.\n";3768  OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";3769  OS << "    return Match_MnemonicFail;\n\n";3770 3771  OS << "  for (const MatchEntry *it = MnemonicRange.first, "3772     << "*ie = MnemonicRange.second;\n";3773  OS << "       it != ie; ++it) {\n";3774  OS << "    const FeatureBitset &RequiredFeatures = "3775        "FeatureBitsets[it->RequiredFeaturesIdx];\n";3776  OS << "    bool HasRequiredFeatures =\n";3777  OS << "      (AvailableFeatures & RequiredFeatures) == RequiredFeatures;\n";3778  OS << "    DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match "3779        "opcode \"\n";3780  OS << "                                          << MII.getName(it->Opcode) "3781        "<< \"\\n\");\n";3782 3783  if (ReportMultipleNearMisses) {3784    OS << "    // Some state to record ways in which this instruction did not "3785          "match.\n";3786    OS << "    NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";3787    OS << "    NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";3788    OS << "    NearMissInfo EarlyPredicateNearMiss = "3789          "NearMissInfo::getSuccess();\n";3790    OS << "    NearMissInfo LatePredicateNearMiss = "3791          "NearMissInfo::getSuccess();\n";3792    OS << "    bool MultipleInvalidOperands = false;\n";3793  }3794 3795  if (HasMnemonicFirst) {3796    OS << "    // equal_range guarantees that instruction mnemonic matches.\n";3797    OS << "    assert(Mnemonic == it->getMnemonic());\n";3798  }3799 3800  // Emit check that the subclasses match.3801  if (!ReportMultipleNearMisses)3802    OS << "    bool OperandsValid = true;\n";3803  if (HasOptionalOperands)3804    OS << "    OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";3805  OS << "    for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")3806     << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")3807     << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";3808  OS << "      auto Formal = "3809     << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";3810  OS << "      DEBUG_WITH_TYPE(\"asm-matcher\",\n";3811  OS << "                      dbgs() << \"  Matching formal operand class \" "3812        "<< getMatchClassName(Formal)\n";3813  OS << "                             << \" against actual operand at index \" "3814        "<< ActualIdx);\n";3815  OS << "      if (ActualIdx < Operands.size())\n";3816  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";3817  OS << "                        Operands[ActualIdx]->print(dbgs(), "3818        "*getContext().getAsmInfo()); dbgs() << "3819        "\"): \");\n";3820  OS << "      else\n";3821  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";3822  OS << "      if (ActualIdx >= Operands.size()) {\n";3823  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand "3824        "index out of range\\n\");\n";3825  if (ReportMultipleNearMisses) {3826    OS << "        bool ThisOperandValid = (Formal == "3827       << "InvalidMatchClass) || "3828          "isSubclass(Formal, OptionalMatchClass);\n";3829    OS << "        if (!ThisOperandValid) {\n";3830    OS << "          if (!OperandNearMiss) {\n";3831    OS << "            // Record info about match failure for later use.\n";3832    OS << "            DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording "3833          "too-few-operands near miss\\n\");\n";3834    OS << "            OperandNearMiss =\n";3835    OS << "                NearMissInfo::getTooFewOperands(Formal, "3836          "it->Opcode);\n";3837    OS << "          } else if (OperandNearMiss.getKind() != "3838          "NearMissInfo::NearMissTooFewOperands) {\n";3839    OS << "            // If more than one operand is invalid, give up on this "3840          "match entry.\n";3841    OS << "            DEBUG_WITH_TYPE(\n";3842    OS << "                \"asm-matcher\",\n";3843    OS << "                dbgs() << \"second invalid operand, giving up on "3844          "this opcode\\n\");\n";3845    OS << "            MultipleInvalidOperands = true;\n";3846    OS << "            break;\n";3847    OS << "          }\n";3848    OS << "        } else {\n";3849    OS << "          DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal "3850          "operand not required\\n\");\n";3851    OS << "          if (isSubclass(Formal, OptionalMatchClass)) {\n";3852    OS << "            OptionalOperandsMask.set(FormalIdx);\n";3853    OS << "          }\n";3854    OS << "        }\n";3855    OS << "        continue;\n";3856  } else {3857    OS << "        if (Formal == InvalidMatchClass) {\n";3858    if (HasOptionalOperands) {3859      OS << "          OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands3860         << ");\n";3861    }3862    OS << "          break;\n";3863    OS << "        }\n";3864    OS << "        if (isSubclass(Formal, OptionalMatchClass)) {\n";3865    if (HasOptionalOperands)3866      OS << "          OptionalOperandsMask.set(FormalIdx);\n";3867    OS << "          continue;\n";3868    OS << "        }\n";3869    OS << "        OperandsValid = false;\n";3870    OS << "        ErrorInfo = ActualIdx;\n";3871    OS << "        break;\n";3872  }3873  OS << "      }\n";3874  OS << "      MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";3875  OS << "      unsigned Diag = validateOperandClass(Actual, Formal, *STI);\n";3876  OS << "      if (Diag == Match_Success) {\n";3877  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\",\n";3878  OS << "                        dbgs() << \"match success using generic "3879        "matcher\\n\");\n";3880  OS << "        ++ActualIdx;\n";3881  OS << "        continue;\n";3882  OS << "      }\n";3883  OS << "      // If the generic handler indicates an invalid operand\n";3884  OS << "      // failure, check for a special case.\n";3885  OS << "      if (Diag != Match_Success) {\n";3886  OS << "        unsigned TargetDiag = validateTargetOperandClass(Actual, "3887        "Formal);\n";3888  OS << "        if (TargetDiag == Match_Success) {\n";3889  OS << "          DEBUG_WITH_TYPE(\"asm-matcher\",\n";3890  OS << "                          dbgs() << \"match success using target "3891        "matcher\\n\");\n";3892  OS << "          ++ActualIdx;\n";3893  OS << "          continue;\n";3894  OS << "        }\n";3895  OS << "        // If the target matcher returned a specific error code use\n";3896  OS << "        // that, else use the one from the generic matcher.\n";3897  OS << "        if (TargetDiag != Match_InvalidOperand && "3898        "HasRequiredFeatures)\n";3899  OS << "          Diag = TargetDiag;\n";3900  OS << "      }\n";3901  OS << "      // If current formal operand wasn't matched and it is optional\n"3902     << "      // then try to match next formal operand\n";3903  OS << "      if (Diag == Match_InvalidOperand "3904     << "&& isSubclass(Formal, OptionalMatchClass)) {\n";3905  if (HasOptionalOperands)3906    OS << "        OptionalOperandsMask.set(FormalIdx);\n";3907  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring "3908        "optional operand\\n\");\n";3909  OS << "        continue;\n";3910  OS << "      }\n";3911 3912  if (ReportMultipleNearMisses) {3913    OS << "      if (!OperandNearMiss) {\n";3914    OS << "        // If this is the first invalid operand we have seen, "3915          "record some\n";3916    OS << "        // information about it.\n";3917    OS << "        DEBUG_WITH_TYPE(\n";3918    OS << "            \"asm-matcher\",\n";3919    OS << "            dbgs()\n";3920    OS << "                << \"operand match failed, recording near-miss with "3921          "diag code \"\n";3922    OS << "                << Diag << \"\\n\");\n";3923    OS << "        OperandNearMiss =\n";3924    OS << "            NearMissInfo::getMissedOperand(Diag, Formal, "3925          "it->Opcode, ActualIdx);\n";3926    OS << "        ++ActualIdx;\n";3927    OS << "      } else {\n";3928    OS << "        // If more than one operand is invalid, give up on this "3929          "match entry.\n";3930    OS << "        DEBUG_WITH_TYPE(\n";3931    OS << "            \"asm-matcher\",\n";3932    OS << "            dbgs() << \"second operand mismatch, skipping this "3933          "opcode\\n\");\n";3934    OS << "        MultipleInvalidOperands = true;\n";3935    OS << "        break;\n";3936    OS << "      }\n";3937    OS << "    }\n\n";3938  } else {3939    OS << "      // If this operand is broken for all of the instances of "3940          "this\n";3941    OS << "      // mnemonic, keep track of it so we can report loc info.\n";3942    OS << "      // If we already had a match that only failed due to a\n";3943    OS << "      // target predicate, that diagnostic is preferred.\n";3944    OS << "      if (!HadMatchOtherThanPredicate &&\n";3945    OS << "          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) "3946          "{\n";3947    OS << "        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "3948          "!= Match_InvalidOperand))\n";3949    OS << "          RetCode = Diag;\n";3950    OS << "        ErrorInfo = ActualIdx;\n";3951    OS << "      }\n";3952    OS << "      // Otherwise, just reject this instance of the mnemonic.\n";3953    OS << "      OperandsValid = false;\n";3954    OS << "      break;\n";3955    OS << "    }\n\n";3956  }3957 3958  if (ReportMultipleNearMisses)3959    OS << "    if (MultipleInvalidOperands) {\n";3960  else3961    OS << "    if (!OperandsValid) {\n";3962  OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "3963        "multiple \"\n";3964  OS << "                                               \"operand mismatches, "3965        "ignoring \"\n";3966  OS << "                                               \"this opcode\\n\");\n";3967  OS << "      continue;\n";3968  OS << "    }\n";3969 3970  // Emit check that the required features are available.3971  OS << "    if (!HasRequiredFeatures) {\n";3972  if (!ReportMultipleNearMisses)3973    OS << "      HadMatchOtherThanFeatures = true;\n";3974  OS << "      FeatureBitset NewMissingFeatures = RequiredFeatures & "3975        "~AvailableFeatures;\n";3976  OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "3977        "features:\";\n";3978  OS << "                      for (unsigned I = 0, E = "3979        "NewMissingFeatures.size(); I != E; ++I)\n";3980  OS << "                        if (NewMissingFeatures[I])\n";3981  OS << "                          dbgs() << ' ' << I;\n";3982  OS << "                      dbgs() << \"\\n\");\n";3983  if (ReportMultipleNearMisses) {3984    OS << "      FeaturesNearMiss = "3985          "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";3986  } else {3987    OS << "      if (NewMissingFeatures.count() <=\n"3988          "          MissingFeatures.count())\n";3989    OS << "        MissingFeatures = NewMissingFeatures;\n";3990    OS << "      continue;\n";3991  }3992  OS << "    }\n";3993  OS << "\n";3994  OS << "    Inst.clear();\n\n";3995  OS << "    Inst.setOpcode(it->Opcode);\n";3996  // Verify the instruction with the target-specific match predicate function.3997  OS << "    // We have a potential match but have not rendered the operands.\n"3998     << "    // Check the target predicate to handle any context sensitive\n"3999        "    // constraints.\n"4000     << "    // For example, Ties that are referenced multiple times must be\n"4001        "    // checked here to ensure the input is the same for each match\n"4002        "    // constraints. If we leave it any later the ties will have been\n"4003        "    // canonicalized\n"4004     << "    unsigned MatchResult;\n"4005     << "    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "4006        "Operands)) != Match_Success) {\n"4007     << "      Inst.clear();\n";4008  OS << "      DEBUG_WITH_TYPE(\n";4009  OS << "          \"asm-matcher\",\n";4010  OS << "          dbgs() << \"Early target match predicate failed with diag "4011        "code \"\n";4012  OS << "                 << MatchResult << \"\\n\");\n";4013  if (ReportMultipleNearMisses) {4014    OS << "      EarlyPredicateNearMiss = "4015          "NearMissInfo::getMissedPredicate(MatchResult);\n";4016  } else {4017    OS << "      RetCode = MatchResult;\n"4018       << "      HadMatchOtherThanPredicate = true;\n"4019       << "      continue;\n";4020  }4021  OS << "    }\n\n";4022 4023  if (ReportMultipleNearMisses) {4024    OS << "    // If we did not successfully match the operands, then we can't "4025          "convert to\n";4026    OS << "    // an MCInst, so bail out on this instruction variant now.\n";4027    OS << "    if (OperandNearMiss) {\n";4028    OS << "      // If the operand mismatch was the only problem, report it as "4029          "a near-miss.\n";4030    OS << "      if (NearMisses && !FeaturesNearMiss && "4031          "!EarlyPredicateNearMiss) {\n";4032    OS << "        DEBUG_WITH_TYPE(\n";4033    OS << "            \"asm-matcher\",\n";4034    OS << "            dbgs()\n";4035    OS << "                << \"Opcode result: one mismatched operand, adding "4036          "near-miss\\n\");\n";4037    OS << "        NearMisses->push_back(OperandNearMiss);\n";4038    OS << "      } else {\n";4039    OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "4040          "multiple \"\n";4041    OS << "                                                 \"types of "4042          "mismatch, so not \"\n";4043    OS << "                                                 \"reporting "4044          "near-miss\\n\");\n";4045    OS << "      }\n";4046    OS << "      continue;\n";4047    OS << "    }\n\n";4048  }4049 4050  // When converting parsed operands to MCInst we need to know whether optional4051  // operands were parsed or not so that we can choose the correct converter4052  // function. We also need to know this when checking tied operand constraints.4053  // DefaultsOffset is an array of deltas between the formal (MCInst) and the4054  // actual (parsed operand array) operand indices. When all optional operands4055  // are present, all elements of the array are zeros. If some of the optional4056  // operands are absent, the array might look like '0, 0, 1, 1, 1, 2, 2, 3',4057  // where each increment in value reflects the absence of an optional operand.4058  if (HasOptionalOperands) {4059    OS << "    unsigned DefaultsOffset[" << (MaxNumOperands + 1)4060       << "] = { 0 };\n";4061    OS << "    assert(OptionalOperandsMask.size() == " << (MaxNumOperands)4062       << ");\n";4063    OS << "    for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)4064       << "; ++i) {\n";4065    OS << "      DefaultsOffset[i + 1] = NumDefaults;\n";4066    OS << "      NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";4067    OS << "    }\n\n";4068  }4069 4070  OS << "    if (matchingInlineAsm) {\n";4071  OS << "      convertToMapAndConstraints(it->ConvertFn, Operands);\n";4072  if (!ReportMultipleNearMisses) {4073    if (HasOptionalOperands) {4074      OS << "      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "4075            "Operands,\n";4076      OS << "                                          DefaultsOffset, "4077            "ErrorInfo))\n";4078    } else {4079      OS << "      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "4080            "Operands,\n";4081      OS << "                                          ErrorInfo))\n";4082    }4083    OS << "        return Match_InvalidTiedOperand;\n";4084    OS << "\n";4085  }4086  OS << "      return Match_Success;\n";4087  OS << "    }\n\n";4088  OS << "    // We have selected a definite instruction, convert the parsed\n"4089     << "    // operands into the appropriate MCInst.\n";4090  if (HasOptionalOperands) {4091    OS << "    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"4092       << "                    OptionalOperandsMask, DefaultsOffset);\n";4093  } else {4094    OS << "    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";4095  }4096  OS << "\n";4097 4098  // Verify the instruction with the target-specific match predicate function.4099  OS << "    // We have a potential match. Check the target predicate to\n"4100     << "    // handle any context sensitive constraints.\n"4101     << "    if ((MatchResult = checkTargetMatchPredicate(Inst)) !="4102     << " Match_Success) {\n"4103     << "      DEBUG_WITH_TYPE(\"asm-matcher\",\n"4104     << "                      dbgs() << \"Target match predicate failed with "4105        "diag code \"\n"4106     << "                             << MatchResult << \"\\n\");\n"4107     << "      Inst.clear();\n";4108  if (ReportMultipleNearMisses) {4109    OS << "      LatePredicateNearMiss = "4110          "NearMissInfo::getMissedPredicate(MatchResult);\n";4111  } else {4112    OS << "      RetCode = MatchResult;\n"4113       << "      HadMatchOtherThanPredicate = true;\n"4114       << "      continue;\n";4115  }4116  OS << "    }\n\n";4117 4118  if (ReportMultipleNearMisses) {4119    OS << "    int NumNearMisses = ((int)(bool)OperandNearMiss +\n";4120    OS << "                         (int)(bool)FeaturesNearMiss +\n";4121    OS << "                         (int)(bool)EarlyPredicateNearMiss +\n";4122    OS << "                         (int)(bool)LatePredicateNearMiss);\n";4123    OS << "    if (NumNearMisses == 1) {\n";4124    OS << "      // We had exactly one type of near-miss, so add that to the "4125          "list.\n";4126    OS << "      assert(!OperandNearMiss && \"OperandNearMiss was handled "4127          "earlier\");\n";4128    OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "4129          "found one type of \"\n";4130    OS << "                                            \"mismatch, so "4131          "reporting a \"\n";4132    OS << "                                            \"near-miss\\n\");\n";4133    OS << "      if (NearMisses && FeaturesNearMiss)\n";4134    OS << "        NearMisses->push_back(FeaturesNearMiss);\n";4135    OS << "      else if (NearMisses && EarlyPredicateNearMiss)\n";4136    OS << "        NearMisses->push_back(EarlyPredicateNearMiss);\n";4137    OS << "      else if (NearMisses && LatePredicateNearMiss)\n";4138    OS << "        NearMisses->push_back(LatePredicateNearMiss);\n";4139    OS << "\n";4140    OS << "      continue;\n";4141    OS << "    } else if (NumNearMisses > 1) {\n";4142    OS << "      // This instruction missed in more than one way, so ignore "4143          "it.\n";4144    OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "4145          "multiple \"\n";4146    OS << "                                               \"types of mismatch, "4147          "so not \"\n";4148    OS << "                                               \"reporting "4149          "near-miss\\n\");\n";4150    OS << "      continue;\n";4151    OS << "    }\n";4152  }4153 4154  // Call the post-processing function, if used.4155  StringRef InsnCleanupFn = AsmParser->getValueAsString("AsmParserInstCleanup");4156  if (!InsnCleanupFn.empty())4157    OS << "    " << InsnCleanupFn << "(Inst);\n";4158 4159  if (HasDeprecation) {4160    OS << "    std::string Info;\n";4161    OS << "    if "4162          "(!getParser().getTargetParser().getTargetOptions()."4163          "MCNoDeprecatedWarn &&\n";4164    OS << "        MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n";4165    OS << "      SMLoc Loc = ((" << Target.getName()4166       << "Operand &)*Operands[0]).getStartLoc();\n";4167    OS << "      getParser().Warning(Loc, Info, {});\n";4168    OS << "    }\n";4169  }4170 4171  if (!ReportMultipleNearMisses) {4172    if (HasOptionalOperands) {4173      OS << "    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "4174            "Operands,\n";4175      OS << "                                         DefaultsOffset, "4176            "ErrorInfo))\n";4177    } else {4178      OS << "    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "4179            "Operands,\n";4180      OS << "                                         ErrorInfo))\n";4181    }4182    OS << "      return Match_InvalidTiedOperand;\n";4183    OS << "\n";4184  }4185 4186  OS << "    DEBUG_WITH_TYPE(\n";4187  OS << "        \"asm-matcher\",\n";4188  OS << "        dbgs() << \"Opcode result: complete match, selecting this "4189        "opcode\\n\");\n";4190  OS << "    return Match_Success;\n";4191  OS << "  }\n\n";4192 4193  if (ReportMultipleNearMisses) {4194    OS << "  // No instruction variants matched exactly.\n";4195    OS << "  return Match_NearMisses;\n";4196  } else {4197    OS << "  // Okay, we had no match.  Try to return a useful error code.\n";4198    OS << "  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";4199    OS << "    return RetCode;\n\n";4200    OS << "  ErrorInfo = 0;\n";4201    OS << "  return Match_MissingFeature;\n";4202  }4203  OS << "}\n\n";4204 4205  if (!Info.OperandMatchInfo.empty())4206    emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,4207                             MaxMnemonicIndex, FeatureBitsets.size(),4208                             HasMnemonicFirst, *AsmParser);4209 4210  OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";4211 4212  OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";4213  OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";4214 4215  emitMnemonicSpellChecker(OS, Target, VariantCount);4216 4217  OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";4218 4219  OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";4220  OS << "#undef GET_MNEMONIC_CHECKER\n\n";4221 4222  emitMnemonicChecker(OS, Target, VariantCount, HasMnemonicFirst,4223                      HasMnemonicAliases);4224 4225  OS << "#endif // GET_MNEMONIC_CHECKER\n\n";4226}4227 4228static TableGen::Emitter::OptClass<AsmMatcherEmitter>4229    X("gen-asm-matcher", "Generate assembly instruction matcher");4230