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1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines wrappers for the Target class and related global10// functionality. This makes it easier to access the data and provides a single11// place that needs to check it for validity. All of these classes abort12// on error conditions.13//14//===----------------------------------------------------------------------===//15 16#ifndef LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H17#define LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H18 19#include "Basic/CodeGenIntrinsics.h"20#include "Basic/SDNodeProperties.h"21#include "CodeGenHwModes.h"22#include "CodeGenInstruction.h"23#include "InfoByHwMode.h"24#include "llvm/ADT/ArrayRef.h"25#include "llvm/ADT/DenseMap.h"26#include "llvm/ADT/SmallVector.h"27#include "llvm/ADT/StringRef.h"28#include "llvm/CodeGenTypes/MachineValueType.h"29#include <cassert>30#include <memory>31#include <string>32#include <vector>33 34namespace llvm {35 36class RecordKeeper;37class Record;38class CodeGenRegBank;39class CodeGenRegister;40class CodeGenRegisterClass;41class CodeGenSchedModels;42class CodeGenSubRegIndex;43 44/// Returns the MVT that the specified TableGen45/// record corresponds to.46MVT getValueType(const Record *Rec);47 48StringRef getEnumName(MVT T);49 50/// getQualifiedName - Return the name of the specified record, with a51/// namespace qualifier if the record contains one.52std::string getQualifiedName(const Record *R);53 54/// CodeGenTarget - This class corresponds to the Target class in the .td files.55///56class CodeGenTarget {57 const RecordKeeper &Records;58 const Record *TargetRec;59 60 mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>61 InstructionMap;62 mutable std::unique_ptr<CodeGenRegBank> RegBank;63 mutable ArrayRef<const Record *> RegAltNameIndices;64 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;65 CodeGenHwModes CGH;66 ArrayRef<const Record *> MacroFusions;67 mutable bool HasVariableLengthEncodings = false;68 69 void ReadInstructions() const;70 void ReadLegalValueTypes() const;71 72 mutable std::unique_ptr<CodeGenSchedModels> SchedModels;73 74 mutable StringRef InstNamespace;75 mutable std::vector<const CodeGenInstruction *> InstrsByEnum;76 mutable CodeGenIntrinsicMap Intrinsics;77 78 mutable unsigned NumPseudoInstructions = 0;79 80public:81 CodeGenTarget(const RecordKeeper &Records);82 ~CodeGenTarget();83 84 const Record *getTargetRecord() const { return TargetRec; }85 StringRef getName() const;86 87 /// getInstNamespace - Return the target-specific instruction namespace.88 ///89 StringRef getInstNamespace() const;90 91 /// getRegNamespace - Return the target-specific register namespace.92 StringRef getRegNamespace() const;93 94 /// getInstructionSet - Return the InstructionSet object.95 ///96 const Record *getInstructionSet() const;97 98 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for99 /// this target.100 ///101 bool getAllowRegisterRenaming() const;102 103 /// getAsmParser - Return the AssemblyParser definition for this target.104 ///105 const Record *getAsmParser() const;106 107 /// getAsmParserVariant - Return the AssemblyParserVariant definition for108 /// this target.109 ///110 const Record *getAsmParserVariant(unsigned i) const;111 112 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition113 /// available for this target.114 ///115 unsigned getAsmParserVariantCount() const;116 117 /// getAsmWriter - Return the AssemblyWriter definition for this target.118 ///119 const Record *getAsmWriter() const;120 121 /// getRegBank - Return the register bank description.122 CodeGenRegBank &getRegBank() const;123 124 /// getRegisterByName - If there is a register with the specific AsmName,125 /// return it.126 const CodeGenRegister *getRegisterByName(StringRef Name) const;127 128 ArrayRef<const Record *> getRegAltNameIndices() const {129 if (RegAltNameIndices.empty())130 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");131 return RegAltNameIndices;132 }133 134 const CodeGenRegisterClass &getRegisterClass(const Record *R) const;135 136 /// Convenience wrapper to avoid hardcoding the name of RegClassByHwMode137 /// everywhere. This is here instead of CodeGenRegBank to avoid the fatal138 /// error that occurs when no RegisterClasses are defined when constructing139 /// the bank.140 ArrayRef<const Record *> getAllRegClassByHwMode() const {141 return Records.getAllDerivedDefinitions("RegClassByHwMode");142 }143 144 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the145 /// specified physical register.146 std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;147 148 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {149 if (LegalValueTypes.empty())150 ReadLegalValueTypes();151 return LegalValueTypes;152 }153 154 /// If \p V is a DefInit that can be interpreted as a RegisterClass (e.g.,155 /// it's a RegisterOperand, or a direct RegisterClass reference), return the156 /// Record for that RegisterClass.157 ///158 /// AssumeRegClassByHwModeIsDefault is a hack which should be removed. It only159 /// happens to be adequate for the current GlobalISel usage.160 const Record *161 getInitValueAsRegClass(const Init *V,162 bool AssumeRegClassByHwModeIsDefault = false) const;163 164 /// If \p V is a DefInit that can be interpreted as a RegisterClassLike,165 /// return the Record. This is used as a convenience function to handle direct166 /// RegisterClass references, or those wrapped in a RegisterOperand.167 const Record *getInitValueAsRegClassLike(const Init *V) const;168 169 CodeGenSchedModels &getSchedModels() const;170 171 const CodeGenHwModes &getHwModes() const { return CGH; }172 173 bool hasMacroFusion() const { return !MacroFusions.empty(); }174 175 ArrayRef<const Record *> getMacroFusions() const { return MacroFusions; }176 177private:178 DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &179 getInstructionMap() const {180 if (InstructionMap.empty())181 ReadInstructions();182 return InstructionMap;183 }184 185public:186 CodeGenInstruction &getInstruction(const Record *InstRec) const {187 auto I = getInstructionMap().find(InstRec);188 assert(I != InstructionMap.end() && "Not an instruction");189 return *I->second;190 }191 192 /// Returns the number of predefined instructions.193 static unsigned getNumFixedInstructions();194 195 /// Return all of the instructions defined by the target, ordered by their196 /// enum value.197 /// The following order of instructions is also guaranteed:198 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;199 /// - pseudo instructions in lexicographical order sorted by name;200 /// - other instructions in lexicographical order sorted by name.201 ArrayRef<const CodeGenInstruction *> getInstructions() const {202 if (InstrsByEnum.empty())203 ComputeInstrsByEnum();204 return InstrsByEnum;205 }206 207 // Functions that return various slices of `getInstructions`, ordered by208 // their enum values.209 ArrayRef<const CodeGenInstruction *> getGenericInstructions() const {210 return getInstructions().take_front(getNumFixedInstructions());211 }212 213 ArrayRef<const CodeGenInstruction *> getTargetInstructions() const {214 return getInstructions().drop_front(getNumFixedInstructions());215 }216 217 ArrayRef<const CodeGenInstruction *> getTargetPseudoInstructions() const {218 return getTargetInstructions().take_front(NumPseudoInstructions);219 }220 221 ArrayRef<const CodeGenInstruction *> getTargetNonPseudoInstructions() const {222 return getTargetInstructions().drop_front(NumPseudoInstructions);223 }224 225 /// Return the integer enum value corresponding to this instruction record.226 unsigned getInstrIntValue(const Record *R) const {227 if (InstrsByEnum.empty())228 ComputeInstrsByEnum();229 return getInstruction(R).EnumVal;230 }231 232 /// Return whether instructions have variable length encodings on this target.233 bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; }234 235 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?236 ///237 bool isLittleEndianEncoding() const;238 239 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit240 /// encodings, reverse the bit order of all instructions.241 void reverseBitsForLittleEndianEncoding();242 243 /// guessInstructionProperties - should we just guess unset instruction244 /// properties?245 bool guessInstructionProperties() const;246 247 const CodeGenIntrinsic &getIntrinsic(const Record *Def) const {248 return Intrinsics[Def];249 }250 251private:252 void ComputeInstrsByEnum() const;253};254 255/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern256/// tablegen class in TargetSelectionDAG.td257class ComplexPattern {258 const Record *Ty;259 unsigned NumOperands;260 std::string SelectFunc;261 std::vector<const Record *> RootNodes;262 unsigned Properties; // Node properties263 unsigned Complexity;264 bool WantsRoot;265 bool WantsParent;266 267public:268 ComplexPattern(const Record *R);269 270 const Record *getValueType() const { return Ty; }271 unsigned getNumOperands() const { return NumOperands; }272 const std::string &getSelectFunc() const { return SelectFunc; }273 ArrayRef<const Record *> getRootNodes() const { return RootNodes; }274 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }275 unsigned getComplexity() const { return Complexity; }276 bool wantsRoot() const { return WantsRoot; }277 bool wantsParent() const { return WantsParent; }278};279 280} // namespace llvm281 282#endif // LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H283