244 lines · cpp
1//===--- InfoByHwMode.cpp -------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// Classes that implement data parameterized by HW modes for instruction9// selection. Currently it is ValueTypeByHwMode (parameterized ValueType),10// and RegSizeInfoByHwMode (parameterized register/spill size and alignment11// data).12//===----------------------------------------------------------------------===//13 14#include "InfoByHwMode.h"15#include "CodeGenRegisters.h"16#include "CodeGenTarget.h"17#include "llvm/ADT/STLExtras.h"18#include "llvm/ADT/Twine.h"19#include "llvm/Support/Debug.h"20#include "llvm/Support/raw_ostream.h"21#include "llvm/TableGen/Record.h"22#include <string>23 24using namespace llvm;25 26std::string llvm::getModeName(unsigned Mode) {27 if (Mode == DefaultMode)28 return "*";29 return (Twine('m') + Twine(Mode)).str();30}31 32ValueTypeByHwMode::ValueTypeByHwMode(const Record *R,33 const CodeGenHwModes &CGH) {34 const HwModeSelect &MS = CGH.getHwModeSelect(R);35 for (const HwModeSelect::PairType &P : MS.Items) {36 auto I = Map.try_emplace(P.first, MVT(llvm::getValueType(P.second)));37 assert(I.second && "Duplicate entry?");38 (void)I;39 }40 if (R->isSubClassOf("PtrValueType"))41 PtrAddrSpace = R->getValueAsInt("AddrSpace");42}43 44ValueTypeByHwMode::ValueTypeByHwMode(const Record *R, MVT T)45 : ValueTypeByHwMode(T) {46 if (R->isSubClassOf("PtrValueType"))47 PtrAddrSpace = R->getValueAsInt("AddrSpace");48}49 50bool ValueTypeByHwMode::operator==(const ValueTypeByHwMode &T) const {51 assert(isValid() && T.isValid() && "Invalid type in assignment");52 bool Simple = isSimple();53 if (Simple != T.isSimple())54 return false;55 if (Simple)56 return getSimple() == T.getSimple();57 58 return Map == T.Map;59}60 61bool ValueTypeByHwMode::operator<(const ValueTypeByHwMode &T) const {62 assert(isValid() && T.isValid() && "Invalid type in comparison");63 // Default order for maps.64 return Map < T.Map;65}66 67MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) {68 auto F = Map.find(Mode);69 if (F != Map.end())70 return F->second;71 // If Mode is not in the map, look up the default mode. If it exists,72 // make a copy of it for Mode and return it.73 auto D = Map.begin();74 if (D != Map.end() && D->first == DefaultMode)75 return Map.try_emplace(Mode, D->second).first->second;76 // If default mode is not present either, use provided Type.77 return Map.try_emplace(Mode, Type).first->second;78}79 80StringRef ValueTypeByHwMode::getMVTName(MVT T) {81 StringRef N = llvm::getEnumName(T.SimpleTy);82 N.consume_front("MVT::");83 return N;84}85 86void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {87 if (isSimple()) {88 OS << getMVTName(getSimple());89 return;90 }91 92 std::vector<const PairType *> Pairs;93 for (const auto &P : Map)94 Pairs.push_back(&P);95 llvm::sort(Pairs, deref<std::less<PairType>>());96 97 OS << '{';98 ListSeparator LS(",");99 for (const PairType *P : Pairs)100 OS << LS << '(' << getModeName(P->first) << ':'101 << getMVTName(P->second).str() << ')';102 OS << '}';103}104 105LLVM_DUMP_METHOD106void ValueTypeByHwMode::dump() const { dbgs() << *this << '\n'; }107 108ValueTypeByHwMode llvm::getValueTypeByHwMode(const Record *Rec,109 const CodeGenHwModes &CGH) {110#ifndef NDEBUG111 if (!Rec->isSubClassOf("ValueType"))112 Rec->dump();113#endif114 assert(Rec->isSubClassOf("ValueType") &&115 "Record must be derived from ValueType");116 if (Rec->isSubClassOf("HwModeSelect"))117 return ValueTypeByHwMode(Rec, CGH);118 return ValueTypeByHwMode(Rec, llvm::getValueType(Rec));119}120 121RegSizeInfo::RegSizeInfo(const Record *R) {122 RegSize = R->getValueAsInt("RegSize");123 SpillSize = R->getValueAsInt("SpillSize");124 SpillAlignment = R->getValueAsInt("SpillAlignment");125}126 127bool RegSizeInfo::operator<(const RegSizeInfo &I) const {128 return std::tie(RegSize, SpillSize, SpillAlignment) <129 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);130}131 132bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const {133 return RegSize <= I.RegSize && SpillAlignment &&134 I.SpillAlignment % SpillAlignment == 0 && SpillSize <= I.SpillSize;135}136 137void RegSizeInfo::writeToStream(raw_ostream &OS) const {138 OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment139 << ']';140}141 142RegSizeInfoByHwMode::RegSizeInfoByHwMode(const Record *R,143 const CodeGenHwModes &CGH) {144 const HwModeSelect &MS = CGH.getHwModeSelect(R);145 for (const HwModeSelect::PairType &P : MS.Items) {146 auto I = Map.try_emplace(P.first, RegSizeInfo(P.second));147 assert(I.second && "Duplicate entry?");148 (void)I;149 }150}151 152bool RegSizeInfoByHwMode::operator<(const RegSizeInfoByHwMode &I) const {153 unsigned M0 = Map.begin()->first;154 return get(M0) < I.get(M0);155}156 157bool RegSizeInfoByHwMode::operator==(const RegSizeInfoByHwMode &I) const {158 unsigned M0 = Map.begin()->first;159 return get(M0) == I.get(M0);160}161 162bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const {163 unsigned M0 = Map.begin()->first;164 return get(M0).isSubClassOf(I.get(M0));165}166 167bool RegSizeInfoByHwMode::hasStricterSpillThan(168 const RegSizeInfoByHwMode &I) const {169 unsigned M0 = Map.begin()->first;170 const RegSizeInfo &A0 = get(M0);171 const RegSizeInfo &B0 = I.get(M0);172 return std::tie(A0.SpillSize, A0.SpillAlignment) >173 std::tie(B0.SpillSize, B0.SpillAlignment);174}175 176void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {177 using PairType = decltype(Map)::value_type;178 std::vector<const PairType *> Pairs;179 for (const auto &P : Map)180 Pairs.push_back(&P);181 llvm::sort(Pairs, deref<std::less<PairType>>());182 183 OS << '{';184 ListSeparator LS(",");185 for (const PairType *P : Pairs)186 OS << LS << '(' << getModeName(P->first) << ':' << P->second << ')';187 OS << '}';188}189 190RegClassByHwMode::RegClassByHwMode(const Record *R, const CodeGenHwModes &CGH,191 const CodeGenRegBank &RegBank) {192 const HwModeSelect &MS = CGH.getHwModeSelect(R);193 194 for (auto [ModeID, RegClassRec] : MS.Items) {195 assert(RegClassRec && RegClassRec->isSubClassOf("RegisterClass") &&196 "Register class must subclass RegisterClass");197 const CodeGenRegisterClass *RegClass = RegBank.getRegClass(RegClassRec);198 if (!Map.try_emplace(ModeID, RegClass).second)199 llvm_unreachable("duplicate entry");200 }201}202 203SubRegRange::SubRegRange(const Record *R) {204 Size = R->getValueAsInt("Size");205 Offset = R->getValueAsInt("Offset");206}207 208SubRegRangeByHwMode::SubRegRangeByHwMode(const Record *R,209 const CodeGenHwModes &CGH) {210 const HwModeSelect &MS = CGH.getHwModeSelect(R);211 for (const HwModeSelect::PairType &P : MS.Items) {212 auto I = Map.try_emplace(P.first, SubRegRange(P.second));213 assert(I.second && "Duplicate entry?");214 (void)I;215 }216}217 218EncodingInfoByHwMode::EncodingInfoByHwMode(const Record *R,219 const CodeGenHwModes &CGH) {220 const HwModeSelect &MS = CGH.getHwModeSelect(R);221 for (const HwModeSelect::PairType &P : MS.Items) {222 assert(P.second && P.second->isSubClassOf("InstructionEncoding") &&223 "Encoding must subclass InstructionEncoding");224 auto I = Map.try_emplace(P.first, P.second);225 assert(I.second && "Duplicate entry?");226 (void)I;227 }228}229 230raw_ostream &llvm::operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {231 T.writeToStream(OS);232 return OS;233}234 235raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfo &T) {236 T.writeToStream(OS);237 return OS;238}239 240raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {241 T.writeToStream(OS);242 return OS;243}244