307 lines · cpp
1//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "Common/CodeGenInstruction.h"10#include "Common/CodeGenTarget.h"11#include "llvm/ADT/IndexedMap.h"12#include "llvm/ADT/SmallVector.h"13#include "llvm/ADT/StringMap.h"14#include "llvm/Support/Debug.h"15#include "llvm/Support/ErrorHandling.h"16#include "llvm/TableGen/Error.h"17#include "llvm/TableGen/Record.h"18#include "llvm/TableGen/TGTimer.h"19#include "llvm/TableGen/TableGenBackend.h"20using namespace llvm;21 22#define DEBUG_TYPE "pseudo-lowering"23 24namespace {25class PseudoLoweringEmitter {26 struct OpData {27 enum MapKind { Operand, Imm, Reg } Kind;28 union {29 unsigned OpNo; // Operand number mapped to.30 uint64_t ImmVal; // Integer immedate value.31 const Record *RegRec; // Physical register.32 };33 };34 struct PseudoExpansion {35 CodeGenInstruction Source; // The source pseudo instruction definition.36 CodeGenInstruction Dest; // The destination instruction to lower to.37 IndexedMap<OpData> OperandMap;38 39 PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,40 IndexedMap<OpData> &m)41 : Source(s), Dest(d), OperandMap(m) {}42 };43 44 const RecordKeeper &Records;45 46 // It's overkill to have an instance of the full CodeGenTarget object,47 // but it loads everything on demand, not in the constructor, so it's48 // lightweight in performance, so it works out OK.49 const CodeGenTarget Target;50 51 SmallVector<PseudoExpansion, 64> Expansions;52 53 void addOperandMapping(unsigned MIOpNo, unsigned NumOps, const Record *Rec,54 const DagInit *Dag, unsigned DagIdx,55 const Record *OpRec, IndexedMap<OpData> &OperandMap,56 const StringMap<unsigned> &SourceOperands,57 const CodeGenInstruction &SourceInsn);58 void evaluateExpansion(const Record *Pseudo);59 void emitLoweringEmitter(raw_ostream &o);60 61public:62 PseudoLoweringEmitter(const RecordKeeper &R) : Records(R), Target(R) {}63 64 /// run - Output the pseudo-lowerings.65 void run(raw_ostream &o);66};67} // End anonymous namespace68 69void PseudoLoweringEmitter::addOperandMapping(70 unsigned MIOpNo, unsigned NumOps, const Record *Rec, const DagInit *Dag,71 unsigned DagIdx, const Record *OpRec, IndexedMap<OpData> &OperandMap,72 const StringMap<unsigned> &SourceOperands,73 const CodeGenInstruction &SourceInsn) {74 const Init *DagArg = Dag->getArg(DagIdx);75 if (const DefInit *DI = dyn_cast<DefInit>(DagArg)) {76 // Physical register reference. Explicit check for the special case77 // "zero_reg" definition.78 if (DI->getDef()->isSubClassOf("Register") ||79 DI->getDef()->getName() == "zero_reg") {80 auto &Entry = OperandMap[MIOpNo];81 Entry.Kind = OpData::Reg;82 Entry.RegRec = DI->getDef();83 return;84 }85 86 if (DI->getDef() != OpRec)87 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +88 "', operand type '" + DI->getDef()->getName() +89 "' does not match expansion operand type '" +90 OpRec->getName() + "'");91 92 StringMap<unsigned>::const_iterator SourceOp =93 SourceOperands.find(Dag->getArgNameStr(DagIdx));94 if (SourceOp == SourceOperands.end())95 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +96 "', output operand '" +97 Dag->getArgNameStr(DagIdx) +98 "' has no matching source operand");99 const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];100 if (NumOps != SrcOpnd.MINumOperands)101 PrintFatalError(102 Rec,103 "In pseudo instruction '" + Rec->getName() + "', output operand '" +104 OpRec->getName() +105 "' has a different number of sub operands than source operand '" +106 SrcOpnd.Rec->getName() + "'");107 108 // Source operand maps to destination operand. Do it for each corresponding109 // MachineInstr operand, not just the first.110 for (unsigned I = 0, E = NumOps; I != E; ++I) {111 auto &Entry = OperandMap[MIOpNo + I];112 Entry.Kind = OpData::Operand;113 Entry.OpNo = SrcOpnd.MIOperandNo + I;114 }115 116 LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << DagIdx117 << "\n");118 } else if (const auto *II = dyn_cast<IntInit>(DagArg)) {119 assert(NumOps == 1);120 auto &Entry = OperandMap[MIOpNo];121 Entry.Kind = OpData::Imm;122 Entry.ImmVal = II->getValue();123 } else if (const auto *BI = dyn_cast<BitsInit>(DagArg)) {124 assert(NumOps == 1);125 auto &Entry = OperandMap[MIOpNo];126 Entry.Kind = OpData::Imm;127 Entry.ImmVal = *BI->convertInitializerToInt();128 } else {129 llvm_unreachable("Unhandled pseudo-expansion argument type!");130 }131}132 133void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {134 LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");135 136 // Validate that the result pattern has the corrent number and types137 // of arguments for the instruction it references.138 const DagInit *Dag = Rec->getValueAsDag("ResultInst");139 assert(Dag && "Missing result instruction in pseudo expansion!");140 LLVM_DEBUG(dbgs() << " Result: " << *Dag << "\n");141 142 const DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());143 if (!OpDef)144 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +145 "', result operator is not a record");146 const Record *Operator = OpDef->getDef();147 if (!Operator->isSubClassOf("Instruction"))148 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +149 "', result operator '" + Operator->getName() +150 "' is not an instruction");151 152 CodeGenInstruction Insn(Operator);153 154 if (Insn.isCodeGenOnly || Insn.isPseudo)155 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +156 "', result operator '" + Operator->getName() +157 "' cannot be a pseudo instruction");158 159 if (Insn.Operands.size() != Dag->getNumArgs())160 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +161 "', result operator '" + Operator->getName() +162 "' has the wrong number of operands");163 164 // If there are more operands that weren't in the DAG, they have to165 // be operands that have default values, or we have an error. Currently,166 // Operands that are a subclass of OperandWithDefaultOp have default values.167 168 // Validate that each result pattern argument has a matching (by name)169 // argument in the source instruction, in either the (outs) or (ins) list.170 // Also check that the type of the arguments match.171 //172 // Record the mapping of the source to result arguments for use by173 // the lowering emitter.174 CodeGenInstruction SourceInsn(Rec);175 StringMap<unsigned> SourceOperands;176 for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands))177 SourceOperands[SrcOp.Name] = Idx;178 179 unsigned NumMIOperands = 0;180 for (const auto &Op : Insn.Operands)181 NumMIOperands += Op.MINumOperands;182 IndexedMap<OpData> OperandMap;183 OperandMap.grow(NumMIOperands);184 185 // FIXME: This pass currently can only expand a pseudo to a single186 // instruction. The pseudo expansion really should take a list of dags, not187 // just a single dag, so we can do fancier things.188 LLVM_DEBUG(dbgs() << " Operand mapping:\n");189 for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) {190 unsigned MIOpNo = DstOp.MIOperandNo;191 192 if (const auto *SubDag = dyn_cast<DagInit>(Dag->getArg(Idx))) {193 if (!DstOp.MIOperandInfo || DstOp.MIOperandInfo->getNumArgs() == 0)194 PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +195 "', operand '" + DstOp.Rec->getName() +196 "' does not have suboperands");197 if (DstOp.MINumOperands != SubDag->getNumArgs()) {198 PrintFatalError(199 Rec, "In pseudo instruction '" + Rec->getName() + "', '" +200 SubDag->getAsString() +201 "' has wrong number of operands for operand type '" +202 DstOp.Rec->getName() + "'");203 }204 for (unsigned I = 0, E = DstOp.MINumOperands; I != E; ++I) {205 auto *OpndRec = cast<DefInit>(DstOp.MIOperandInfo->getArg(I))->getDef();206 addOperandMapping(MIOpNo + I, 1, Rec, SubDag, I, OpndRec, OperandMap,207 SourceOperands, SourceInsn);208 }209 } else {210 addOperandMapping(MIOpNo, DstOp.MINumOperands, Rec, Dag, Idx, DstOp.Rec,211 OperandMap, SourceOperands, SourceInsn);212 }213 }214 215 Expansions.emplace_back(SourceInsn, Insn, OperandMap);216}217 218void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {219 // Emit file header.220 emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);221 222 o << "bool " << Target.getName() + "AsmPrinter::\n"223 << "lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst) {\n";224 225 if (!Expansions.empty()) {226 o << " Inst.clear();\n"227 << " switch (MI->getOpcode()) {\n"228 << " default: return false;\n";229 for (auto &Expansion : Expansions) {230 CodeGenInstruction &Source = Expansion.Source;231 CodeGenInstruction &Dest = Expansion.Dest;232 o << " case " << Source.Namespace << "::" << Source.getName() << ": {\n"233 << " MCOperand MCOp;\n"234 << " Inst.setOpcode(" << Dest.Namespace << "::" << Dest.getName()235 << ");\n";236 237 // Copy the operands from the source instruction.238 // FIXME: Instruction operands with defaults values (predicates and cc_out239 // in ARM, for example shouldn't need explicit values in the240 // expansion DAG.241 for (const auto &DestOperand : Dest.Operands) {242 o << " // Operand: " << DestOperand.Name << "\n";243 unsigned MIOpNo = DestOperand.MIOperandNo;244 for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {245 switch (Expansion.OperandMap[MIOpNo + i].Kind) {246 case OpData::Operand:247 o << " lowerOperand(MI->getOperand("248 << Expansion.OperandMap[MIOpNo + i].OpNo << "), MCOp);\n"249 << " Inst.addOperand(MCOp);\n";250 break;251 case OpData::Imm:252 o << " Inst.addOperand(MCOperand::createImm("253 << Expansion.OperandMap[MIOpNo + i].ImmVal << "));\n";254 break;255 case OpData::Reg: {256 const Record *Reg = Expansion.OperandMap[MIOpNo + i].RegRec;257 o << " Inst.addOperand(MCOperand::createReg(";258 // "zero_reg" is special.259 if (Reg->getName() == "zero_reg")260 o << "0";261 else262 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();263 o << "));\n";264 break;265 }266 }267 }268 }269 if (Dest.Operands.isVariadic) {270 unsigned LastOpNo = 0;271 for (const auto &Op : Source.Operands)272 LastOpNo += Op.MINumOperands;273 o << " // variable_ops\n";274 o << " for (unsigned i = " << LastOpNo275 << ", e = MI->getNumOperands(); i != e; ++i)\n"276 << " if (lowerOperand(MI->getOperand(i), MCOp))\n"277 << " Inst.addOperand(MCOp);\n";278 }279 o << " break;\n"280 << " }\n";281 }282 o << " }\n return true;";283 } else {284 o << " return false;";285 }286 287 o << "\n}\n\n";288}289 290void PseudoLoweringEmitter::run(raw_ostream &OS) {291 StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};292 293 // Process the pseudo expansion definitions, validating them as we do so.294 TGTimer &Timer = Records.getTimer();295 Timer.startTimer("Process definitions");296 for (const Record *Inst : Records.getAllDerivedDefinitions(Classes))297 evaluateExpansion(Inst);298 299 // Generate expansion code to lower the pseudo to an MCInst of the real300 // instruction.301 Timer.startTimer("Emit expansion code");302 emitLoweringEmitter(OS);303}304 305static TableGen::Emitter::OptClass<PseudoLoweringEmitter>306 X("gen-pseudo-lowering", "Generate pseudo instruction lowering");307