443 lines · cpp
1//===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This tablegen backend is responsible for emitting a description of a target10// register bank for a code generator.11//12//===----------------------------------------------------------------------===//13 14#include "Common/CodeGenRegisters.h"15#include "Common/CodeGenTarget.h"16#include "Common/InfoByHwMode.h"17#include "llvm/ADT/BitVector.h"18#include "llvm/Support/Debug.h"19#include "llvm/Support/MathExtras.h"20#include "llvm/TableGen/Error.h"21#include "llvm/TableGen/Record.h"22#include "llvm/TableGen/TGTimer.h"23#include "llvm/TableGen/TableGenBackend.h"24 25#define DEBUG_TYPE "register-bank-emitter"26 27using namespace llvm;28 29namespace {30class RegisterBank {31 32 /// A vector of register classes that are included in the register bank.33 using RegisterClassesTy = std::vector<const CodeGenRegisterClass *>;34 35private:36 const Record &TheDef;37 38 /// The register classes that are covered by the register bank.39 RegisterClassesTy RCs;40 41 /// The register class with the largest register size.42 std::vector<const CodeGenRegisterClass *> RCsWithLargestRegSize;43 44public:45 RegisterBank(const Record &TheDef, unsigned NumModeIds)46 : TheDef(TheDef), RCsWithLargestRegSize(NumModeIds) {}47 48 /// Get the human-readable name for the bank.49 StringRef getName() const { return TheDef.getValueAsString("Name"); }50 /// Get the name of the enumerator in the ID enumeration.51 std::string getEnumeratorName() const {52 return (TheDef.getName() + "ID").str();53 }54 55 /// Get the name of the array holding the register class coverage data;56 std::string getCoverageArrayName() const {57 return (TheDef.getName() + "CoverageData").str();58 }59 60 /// Get the name of the global instance variable.61 StringRef getInstanceVarName() const { return TheDef.getName(); }62 63 const Record &getDef() const { return TheDef; }64 65 /// Get the register classes listed in the RegisterBank.RegisterClasses field.66 std::vector<const CodeGenRegisterClass *>67 getExplicitlySpecifiedRegisterClasses(68 const CodeGenRegBank &RegisterClassHierarchy) const {69 std::vector<const CodeGenRegisterClass *> RCs;70 for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))71 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));72 return RCs;73 }74 75 /// Add a register class to the bank without duplicates.76 void addRegisterClass(const CodeGenRegisterClass *RC) {77 if (llvm::is_contained(RCs, RC))78 return;79 80 // FIXME? We really want the register size rather than the spill size81 // since the spill size may be bigger on some targets with82 // limited load/store instructions. However, we don't store the83 // register size anywhere (we could sum the sizes of the subregisters84 // but there may be additional bits too) and we can't derive it from85 // the VT's reliably due to Untyped.86 unsigned NumModeIds = RCsWithLargestRegSize.size();87 for (unsigned M = 0; M < NumModeIds; ++M) {88 if (RCsWithLargestRegSize[M] == nullptr)89 RCsWithLargestRegSize[M] = RC;90 else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize <91 RC->RSI.get(M).SpillSize)92 RCsWithLargestRegSize[M] = RC;93 assert(RCsWithLargestRegSize[M] && "RC was nullptr?");94 }95 96 RCs.emplace_back(RC);97 }98 99 const CodeGenRegisterClass *getRCWithLargestRegSize(unsigned HwMode) const {100 return RCsWithLargestRegSize[HwMode];101 }102 103 iterator_range<RegisterClassesTy::const_iterator> register_classes() const {104 return RCs;105 }106};107 108class RegisterBankEmitter {109private:110 const CodeGenTarget Target;111 const RecordKeeper &Records;112 113 void emitHeader(raw_ostream &OS, const StringRef TargetName,114 ArrayRef<RegisterBank> Banks);115 void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,116 ArrayRef<RegisterBank> Banks);117 void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,118 ArrayRef<RegisterBank> Banks);119 120public:121 RegisterBankEmitter(const RecordKeeper &R) : Target(R), Records(R) {}122 123 void run(raw_ostream &OS);124};125 126} // end anonymous namespace127 128/// Emit code to declare the ID enumeration and external global instance129/// variables.130void RegisterBankEmitter::emitHeader(raw_ostream &OS,131 const StringRef TargetName,132 ArrayRef<RegisterBank> Banks) {133 // <Target>RegisterBankInfo.h134 OS << "namespace llvm {\n"135 << "namespace " << TargetName << " {\n"136 << "enum : unsigned {\n";137 138 OS << " InvalidRegBankID = ~0u,\n";139 unsigned ID = 0;140 for (const auto &Bank : Banks)141 OS << " " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";142 OS << " NumRegisterBanks,\n"143 << "};\n"144 << "} // end namespace " << TargetName << "\n"145 << "} // end namespace llvm\n";146}147 148/// Emit declarations of the <Target>GenRegisterBankInfo class.149void RegisterBankEmitter::emitBaseClassDefinition(150 raw_ostream &OS, const StringRef TargetName, ArrayRef<RegisterBank> Banks) {151 OS << "private:\n"152 << " static const RegisterBank *RegBanks[];\n"153 << " static const unsigned Sizes[];\n\n"154 << "public:\n"155 << " const RegisterBank &getRegBankFromRegClass(const "156 "TargetRegisterClass &RC, LLT Ty) const override;\n"157 << "protected:\n"158 << " " << TargetName << "GenRegisterBankInfo(unsigned HwMode = 0);\n"159 << "\n";160}161 162/// Visit each register class belonging to the given register bank.163///164/// A class belongs to the bank iff any of these apply:165/// * It is explicitly specified166/// * It is a subclass of a class that is a member.167/// * It is a class containing subregisters of the registers of a class that168/// is a member. This is known as a subreg-class.169///170/// This function must be called for each explicitly specified register class.171///172/// \param RC The register class to search.173/// \param Kind A debug string containing the path the visitor took to reach RC.174/// \param VisitFn The action to take for each class visited. It may be called175/// multiple times for a given class if there are multiple paths176/// to the class.177static void visitRegisterBankClasses(178 const CodeGenRegBank &RegisterClassHierarchy,179 const CodeGenRegisterClass *RC, const Twine &Kind,180 std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,181 DenseSet<const CodeGenRegisterClass *> &VisitedRCs) {182 183 // Make sure we only visit each class once to avoid infinite loops.184 if (!VisitedRCs.insert(RC).second)185 return;186 187 // Visit each explicitly named class.188 VisitFn(RC, Kind.str());189 190 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {191 std::string TmpKind =192 (Kind + " (" + PossibleSubclass.getName() + ")").str();193 194 // Visit each subclass of an explicitly named class.195 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))196 visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,197 TmpKind + " " + RC->getName() + " subclass",198 VisitFn, VisitedRCs);199 200 // Visit each class that contains only subregisters of RC with a common201 // subregister-index.202 //203 // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in204 // PossibleSubclass for all registers Reg from RC using any205 // subregister-index SubReg206 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {207 BitVector BV(RegisterClassHierarchy.getRegClasses().size());208 PossibleSubclass.getSuperRegClasses(&SubIdx, BV);209 if (BV.test(RC->EnumValue)) {210 std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +211 " class-with-subregs: " + RC->getName())212 .str();213 VisitFn(&PossibleSubclass, TmpKind2);214 }215 }216 }217}218 219void RegisterBankEmitter::emitBaseClassImplementation(220 raw_ostream &OS, StringRef TargetName, ArrayRef<RegisterBank> Banks) {221 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();222 const CodeGenHwModes &CGH = Target.getHwModes();223 224 OS << "namespace llvm {\n"225 << "namespace " << TargetName << " {\n";226 for (const auto &Bank : Banks) {227 std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(228 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);229 230 for (const auto &RC : Bank.register_classes())231 RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);232 233 OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";234 unsigned LowestIdxInWord = 0;235 for (const auto &RCs : RCsGroupedByWord) {236 OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)237 << "\n";238 for (const auto &RC : RCs) {239 OS << " (1u << (" << RC->getQualifiedIdName() << " - "240 << LowestIdxInWord << ")) |\n";241 }242 OS << " 0,\n";243 LowestIdxInWord += 32;244 }245 OS << "};\n";246 }247 OS << "\n";248 249 for (const auto &Bank : Banks) {250 std::string QualifiedBankID =251 (TargetName + "::" + Bank.getEnumeratorName()).str();252 OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "253 << QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "254 << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()255 << ", /* NumRegClasses */ "256 << RegisterClassHierarchy.getRegClasses().size() << ");\n";257 }258 OS << "} // end namespace " << TargetName << "\n"259 << "\n";260 261 OS << "const RegisterBank *" << TargetName262 << "GenRegisterBankInfo::RegBanks[] = {\n";263 for (const auto &Bank : Banks)264 OS << " &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";265 OS << "};\n\n";266 267 unsigned NumModeIds = CGH.getNumModeIds();268 OS << "const unsigned " << TargetName << "GenRegisterBankInfo::Sizes[] = {\n";269 for (unsigned M = 0; M < NumModeIds; ++M) {270 OS << " // Mode = " << M << " (";271 if (M == DefaultMode)272 OS << "Default";273 else274 OS << CGH.getMode(M).Name;275 OS << ")\n";276 for (const auto &Bank : Banks) {277 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M);278 unsigned Size = RC.RSI.get(M).SpillSize;279 OS << " " << Size << ",\n";280 }281 }282 OS << "};\n\n";283 284 OS << TargetName << "GenRegisterBankInfo::" << TargetName285 << "GenRegisterBankInfo(unsigned HwMode)\n"286 << " : RegisterBankInfo(RegBanks, " << TargetName287 << "::NumRegisterBanks, Sizes, HwMode) {\n"288 << " // Assert that RegBank indices match their ID's\n"289 << "#ifndef NDEBUG\n"290 << " for (auto RB : enumerate(RegBanks))\n"291 << " assert(RB.index() == RB.value()->getID() && \"Index != ID\");\n"292 << "#endif // NDEBUG\n"293 << "}\n";294 295 uint32_t NumRegBanks = Banks.size();296 uint32_t BitSize = NextPowerOf2(Log2_32(NumRegBanks));297 uint32_t ElemsPerWord = 32 / BitSize;298 uint32_t BitMask = (1 << BitSize) - 1;299 bool HasAmbigousOrMissingEntry = false;300 struct Entry {301 std::string RCIdName;302 std::string RBIdName;303 };304 SmallVector<Entry, 0> Entries;305 for (const auto &Bank : Banks) {306 for (const auto *RC : Bank.register_classes()) {307 if (RC->EnumValue >= Entries.size())308 Entries.resize(RC->EnumValue + 1);309 Entry &E = Entries[RC->EnumValue];310 E.RCIdName = RC->getIdName();311 if (!E.RBIdName.empty()) {312 HasAmbigousOrMissingEntry = true;313 E.RBIdName = "InvalidRegBankID";314 } else {315 E.RBIdName = (TargetName + "::" + Bank.getEnumeratorName()).str();316 }317 }318 }319 for (auto &E : Entries) {320 if (E.RBIdName.empty()) {321 HasAmbigousOrMissingEntry = true;322 E.RBIdName = "InvalidRegBankID";323 }324 }325 OS << "const RegisterBank &\n"326 << TargetName327 << "GenRegisterBankInfo::getRegBankFromRegClass"328 "(const TargetRegisterClass &RC, LLT) const {\n";329 if (HasAmbigousOrMissingEntry) {330 OS << " constexpr uint32_t InvalidRegBankID = uint32_t("331 << TargetName + "::InvalidRegBankID) & " << BitMask << ";\n";332 }333 unsigned TableSize =334 Entries.size() / ElemsPerWord + ((Entries.size() % ElemsPerWord) > 0);335 OS << " static const uint32_t RegClass2RegBank[" << TableSize << "] = {\n";336 uint32_t Shift = 32 - BitSize;337 bool First = true;338 std::string TrailingComment;339 for (auto &E : Entries) {340 Shift += BitSize;341 if (Shift == 32) {342 Shift = 0;343 if (First)344 First = false;345 else346 OS << ',' << TrailingComment << '\n';347 } else {348 OS << " |" << TrailingComment << '\n';349 }350 OS << " ("351 << (E.RBIdName.empty()352 ? "InvalidRegBankID"353 : Twine("uint32_t(").concat(E.RBIdName).concat(")").str())354 << " << " << Shift << ')';355 if (!E.RCIdName.empty())356 TrailingComment = " // " + E.RCIdName;357 else358 TrailingComment = "";359 }360 OS << TrailingComment361 << "\n };\n"362 " const unsigned RegClassID = RC.getID();\n"363 " if (LLVM_LIKELY(RegClassID < "364 << Entries.size()365 << ")) {\n"366 " unsigned RegBankID = (RegClass2RegBank[RegClassID / "367 << ElemsPerWord << "] >> ((RegClassID % " << ElemsPerWord << ") * "368 << BitSize << ")) & " << BitMask << ";\n";369 if (HasAmbigousOrMissingEntry) {370 OS << " if (RegBankID != InvalidRegBankID)\n"371 " return getRegBank(RegBankID);\n";372 } else {373 OS << " return getRegBank(RegBankID);\n";374 }375 OS << " }\n"376 " llvm_unreachable(llvm::Twine(\"Target needs to handle register "377 "class ID "378 "0x\").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());\n"379 "}\n";380 381 OS << "} // end namespace llvm\n";382}383 384void RegisterBankEmitter::run(raw_ostream &OS) {385 StringRef TargetName = Target.getName();386 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();387 const CodeGenHwModes &CGH = Target.getHwModes();388 389 TGTimer &Timer = Records.getTimer();390 Timer.startTimer("Analyze records");391 std::vector<RegisterBank> Banks;392 for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {393 DenseSet<const CodeGenRegisterClass *> VisitedRCs;394 RegisterBank Bank(*V, CGH.getNumModeIds());395 396 for (const CodeGenRegisterClass *RC :397 Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {398 visitRegisterBankClasses(399 RegisterClassHierarchy, RC, "explicit",400 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {401 LLVM_DEBUG(dbgs()402 << "Added " << RC->getName() << "(" << Kind << ")\n");403 Bank.addRegisterClass(RC);404 },405 VisitedRCs);406 }407 408 Banks.push_back(Bank);409 }410 411 // Warn about ambiguous MIR caused by register bank/class name clashes.412 Timer.startTimer("Warn ambiguous");413 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {414 for (const auto &Bank : Banks) {415 if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {416 PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "417 "distinct from register classes "418 "to avoid ambiguous MIR");419 PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");420 PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");421 }422 }423 }424 425 Timer.startTimer("Emit output");426 emitSourceFileHeader("Register Bank Source Fragments", OS);427 OS << "#ifdef GET_REGBANK_DECLARATIONS\n"428 << "#undef GET_REGBANK_DECLARATIONS\n";429 emitHeader(OS, TargetName, Banks);430 OS << "#endif // GET_REGBANK_DECLARATIONS\n\n"431 << "#ifdef GET_TARGET_REGBANK_CLASS\n"432 << "#undef GET_TARGET_REGBANK_CLASS\n";433 emitBaseClassDefinition(OS, TargetName, Banks);434 OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"435 << "#ifdef GET_TARGET_REGBANK_IMPL\n"436 << "#undef GET_TARGET_REGBANK_IMPL\n";437 emitBaseClassImplementation(OS, TargetName, Banks);438 OS << "#endif // GET_TARGET_REGBANK_IMPL\n";439}440 441static TableGen::Emitter::OptClass<RegisterBankEmitter>442 X("gen-register-bank", "Generate registers bank descriptions");443